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參數(shù)資料
| 型號： | LM2893 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LM1893/LM2893 Carrier-Current Transceiver |
| 中文描述： | LM1893/LM2893載波電流收發(fā)器 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 576K |
| 代理商： | LM2893 |
Receiver Electrical Characteristics
(Note 3). The test conditions are: V
a
e
18 V, F
O
e
125 kHz,
g
2.2%
deviation FSK, F
DATA
e
2.4 kHz, V
IN
e
100 mVpp, in the receive mode, unless otherwise noted.
Test
Limit
(Note 4)
Design
Limit
(Note 5)
Limit
Units
Y
Parameter
Conditions
Typical
25
Supply voltage, V
a
, range
Functional receiver (Note 7)
12
37
13
30
13.5
28
V min.
V max.
26
Supply current, I
QT
I
QT
is pin 15 (V
a
) plus pin 10
(Carrier I/O) current. 2.4 k
X
Pin 13 to GND.
11
5
14
mA min.
mA max.
27
Carrier I/O input resistance, R
10
Pin 10
19.5
14
30
k
X
min.
k
X
max.
28
Max. data rate, F
MD
Functional receiver (Note 7), C
F
e
100 pF,
R
F
e
0
X
, no tank,
2.4 kHz
e
4.8 kBaud
C
F
e
100 pF, R
F
e
0
X
C
F
e
100 pF, R
F
e
0
X
10
4.8
2.4
kBaud
29
PLL capture range, F
C
g
40
g
15
g
10
% min.
30
PLL lock range, F
L
g
45
g
15
% min.
31
Receiver input sensitivity, S
IN
For a functional receiver (Note 8)
Referred to chip side (pin 10)
of the line-coupling XFMR: F
O
e
50 kHz
1.8
2.0
1.4
0.26
0.29
0.20
10
12
mV
RMS
mV
RMS
mV
RMS
mV
RMS
mV
RMS
mV
RMS
F
O
e
300 kHz
Referred to line side of XFMR:
(assuming a 7.07:1 XFMR) F
O
e
50 kHz
F
O
e
300 kHz
32
Tolerable input dc voltage offset
range, V
INDC
Pin 10 lower than pin 15 by V
INDC
2
0.1
V max.
33
Data Out. breakdown voltage
Pin 12, leakage I
s
20
m
A
70
55
V min.
34
Data Out. low output, V
OL
Pin 12, sat. voltage at I
OL
e
2 mA
0.15
0.4
V max.
35
Impulse noise filter current, I
I
Pin 13 charge and discharge current
g
55
g
45
g
85
m
A min.
m
A max.
36
Offset hold cap. bias voltage, V
CM
Pin 6
2.0
1.3
3.5
V min.
V max.
37
Offset hold capacitor max. drive
current, I
MCM
Pin 6. V(pin 3)
b
V(pin 4)
e
g
250 mV
g
55
g
25
g
80
b
20
m
A min.
m
A max.
38
Offset hold bias current, I
OHB
Pin 6, TX mode. Bias pin 6 as it self-
biased during test 31.
b
0.5
b
40
40
nA min.
nA max.
39
Phase comparator current, I
PC
Bias pins 3 and 4 at 8.5 V
I
PC
e
I(pin 3)
a
I(pin 4), TX mode
100
50
200
m
A min.
m
A max.
40
Phase detector output resistance,
R
PD
Pins 3 and 4.
R
PD
e
(V
@
100
m
A
b
V
@
50
m
A)/(50
m
A)
10
6
k
X
min.
k
X
max.
18
41
Phase detector demodulated output
voltage, V
PD
Pin 3 to 4, measured after filtering
out the 2F
O
component
V
PIN3
b
V
PIN4
e
g
V
WINDOW
a
DC offset
Drive for
g
1
m
A pin 6 current
C
L
e
0.1
m
F. PSRR
e
CMRR. 120 Hz
100
60
180
mVpp min.
mVpp max.
42
Fast offset cancel voltage ‘‘window’’
-to-V
PD
ratio, V
W
/V
PD
0.95
0.70
1.20
V/V min.
V/V max.
43
Power supply rejection, PSRR
80
dB min.
Note 1:
More accurately, the maximum voltage allowed on pin 10 is V
OC
, and V
OC
ranges from 41 to 50V. Also, transients may reach above 60V; see the transient
peak voltage characteristic curve.
Note 2:
The maximum power dissipation rating should be derated for device operation above 25
§
C to insure that the junction temperature remains below the
maximum rating. Use a
i
JA
of 75
§
C/W for the N package using a socket in still air (which is the worst case). Consult the Application Information section for more
detail.
Note 3:
The
boldface
values apply over the full junction temperature range for the specified supply voltage range. All other numbers apply at T
A
e
T
J
e
25
§
C. Pin
numbers refer to LM1893. LM2893 tested by shorting Carrier In to Carrier Out and testing it as an LM1893.
Note 4:
Guaranteed and 100% production tested.
Note 5:
Guaranteed (but not 100% production tested) over the temperature and supply voltage ranges. These limits are not used to calculate outgoing quality
levels.
Note 6:
Total harmonic distortion is measured using THD
e
[
I
RMS
(all components at or above 2F
O
)
]
/
[
I
RMS
(fundamental)
]
.
Note 7:
Receiver function is defined as the error-free passage of 1 cycle of 50% duty-cycle 2.4 kHz square-wave data (2 sequential 208
m
S bits), with the first bit
being a ‘‘1.’’ All of the data transitions (edges) must fall within
g
10% (
g
20.8
m
s) of their noise-free positions. RX time delay is minimized by using no impulse noise
filter cap. C
I
for this test.
Note 8:
During the sensitivity check, note 7 requirements are followed with these exceptions: (1) data rate F
DATA
e
1.2 kHz, (2) all of the data transitions must fall
within
g
20% (
g
41.6
m
s) of their noise-free positions, and (3), a time-domain filter capacitor (C
I
) is used. The time delay of C
I
is
(/2
bit, or 208
m
s. (C
I
is
approximately 6200 pF).
Note 9:
For TTL compatibility use a pull-up resistor to increase min. V
OH
to above 2.8 V.
3
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