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參數(shù)資料
| 型號： | LM2744 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller with External Reference |
| 中文描述： | 低壓N溝道MOSFET同步降壓穩(wěn)壓控制器與外部參考 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 663K |
| 代理商： | LM2744 |
Application Information
(Continued)
The power stage modulator provides a DC gain A
DC
that is
equal to the input voltage divided by the peak-to-peak value
of the PWM ramp. This ramp is 1.0VP-P for the LM2744. The
inductor and output capacitor create a double pole at fre-
quency f
DP
, and the capacitor ESR and capacitance create a
single zero at frequency f
ESR
. For this example, with V
IN
=
3.3V, these quantities are:
In the equation for f
DP
, the variable R
L
is the power stage
resistance, and represents the inductor DCR plus the on
resistance of the high-side MOSFET. R
O
is the output volt-
age divided by output current. The power stage transfer
function G
is given by the following equation, and
Figure
12
shows Bode plots of the phase and gain in this example.
a = LC
O
(R
O
+ R
C
)
b = L + C
O
(R
O
R
L
+ R
O
R
C
+ R
C
R
L
)
c = R
O
+ R
L
The double pole at 4.5kHz causes the phase to drop to
approximately -130 at around 10kHz. The ESR zero, at
20.3kHz, provides a +90 boost that prevents the phase from
dropping to -180
o
. If this loop were left uncompensated, the
bandwidth would be approximately 10kHz and the phase
margin 53. In theory, the loop would be stable, but would
suffer from poor DC regulation (due to the low DC gain) and
would be slow to respond to load transients (due to the low
bandwidth.) In practice, the loop could easily become un-
stable due to tolerances in the output inductor, capacitor, or
changes in output current, or input voltage. Therefore, the
loop is compensated using the error amplifier and a few
passive components.
For this example, a Type III, or three-pole-two-zero approach
gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including
Type III, a single pole is placed at the origin to boost DC gain
as high as possible. Two zeroes f
and f
are placed at the
double pole frequency to cancel the double pole phase lag.
Then, a pole, f
P1
is placed at the frequency of the ESR zero.
A final pole f
is placed at one-half of the switching fre-
quency. The gain of the error amplifier transfer function is
selected to give the best bandwidth possible without violat-
ing the Nyquist stability criteria. In practice, a good crossover
20106069
20106070
FIGURE 12. Power Stage Gain and Phase
L
www.national.com
16
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