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參數(shù)資料
| 型號： | LM2630MTC-ADJX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LM2630MTC-ADJX |
ripple requirement. A reasonable value is setting the ripple
current to be 30% of the dc output current. Since the ripple
current increase with the input voltage, the maximum input
voltage is always used to determine the inductance. The dc
resistance of the inductor is a key parameter for the efficiency.
Lower dc resistance is available with a bigger winding area.
A good tradeoff between the efficiency and the core size is
letting the inductor copper loss equal to 2% of the output
power.
INPUT CAPACITOR
A low ESR aluminum or tantalum capacitor is needed be-
tween the drain of the high-side MOSFET and ground to
prevent large voltage transients from appearing at the input.
The capacitor is selected based on the RMS current and volt-
age requirements. The RMS current is given by:
The RMS current reaches its maximum (I
OUT/2) when VIN
equals 2V
OUT. A parallel of several capacitors may be re-
quired to meet the RMS current rating. For an aluminum
capacitor, the voltage rating should be at least 25% higher
than the maximum input voltage. If a tantalum capacitor is
used, the voltage rating should be about twice the maximum
input voltage. The tantalum capacitor should also be surge
current tested by the manufacturer. It is also recommended
to put a small ceramic capacitor (0.1 F) between the V
IN pin
and ground.
OUTPUT CAPACITOR
The selection of C
OUT is driven by the maximum allowable
output voltage ripple. The output ripple in FPWM mode is ap-
proximated by:
The ESR term plays the dominant role in determining the
voltage ripple. Low ESR aluminum electrolytic or tantalum
capacitors (such as Nichicon PL series, Sanyo OS-CON,
Sprague 593D, 594D, and AVX TPS) are recommended.
Electrolytic capacitors are not recommended for temperature
below 25°C since their ESR rises dramatically at cold tem-
perature. Tantalum capacitors have a much better ESR spec-
ification at cold temperatures and are preferred for low
temperature applications.
POWER MOSFETS
Two N-channel logic-level MOSFETs are required for this ap-
plication. MOSFETs with low on-resistance and total gate
charge are recommended to achieve high efficiency. The
drain-source breakdown voltage ratings are recommended to
be 1.2 times the maximum input voltage.
SCHOTTKY DIODE D
1
The Schottky diode D
1 is used to prevent the intrinsic body
diode of the low-side MOSFET Q
2 from conducting during the
dead time when both MOSFETs are off. Since the forward
voltage of D
1 is less than the body diode, efficiency can be
improved. The breakdown voltage rating of D
1 is preferred to
be 25% higher than the maximum input voltage. Since D
1 is
only on for a short period of time (about 200 ns each cycle),
the average current rating for D
1 only requires to be higher
than 30% of the maximum output current. It is important to
place D
1 very close to the drain and source of Q2, extra par-
asitic inductance in the parallel loop will slow the turn-on of
D
1 and direct the current through the body diode of Q2.
R
1 AND R2 (PROGRAMMING OUTPUT VOLTAGE)
Use the following formula to select the appropriate resistor
values:
V
OUT = VREF(1 + R1/R2)
where V
REF = 1.238V
Select a value for R
2 between 10kΩ and 100kΩ. (Use 1% or
higher accuracy metal film resistors).
CURRENT SENSE RESISTOR
The value of the sense resistor is determined by the minimum
current limit voltage and the maximum peak current. It can be
calculated as follows:
where TF is the tolerance factor of the sense resistor.
PCB LAYOUT CONSIDERATIONS
Layout is critical to reduce noises and ensure specified per-
formance. The important guidelines are listed as follows:
1.
Minimize the parasitic inductance in the loop of input
capacitors and MOSFETS: Q1, Q2 by using wide and
short traces. This is important because the rapidly
switching current, together with wiring inductance can
generate large voltage spikes which can cause noise
problems.
2.
Always minimize the high-current ground traces: such as
the traces from PGND pin to the source of Q2, then to
the negative terminals of the output capacitors.
3.
Use dedicated (Kelvin sense) and short traces from CSH,
CSL pins to the sense resistor, R3. Keep these traces
away from noise traces (such as SW trace, and gate
traces).
4.
Minimize the traces connecting Q2 and the Schottky
diode. Any parasitic inductance in the loop can delay the
turn-on of the Schottky diode, which diminishes the
efficiency gain from adding D1.
5.
Minimize the traces from drivers (HDRV pin and LDRV
pin) to the MOSFETs gates.
6.
Minimize the trace from the center of the output resistor
divider to the FB pin and keep it away from noise sources
to avoid noise pickup. A dedicated sense trace
(separated from the power trace) can be used to connect
the top of the resistor divider to the output. The sense
trace ensures tight regulation at the output.
www.national.com
10
100120 Version 9 Revision 2
Print Date/Time: 2011/08/25 17:11:52
LM2630
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