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Operation (Continued)
on until the end of the cycle or until the inductor current
reaches zero; when this occurs, the zero cross detector will
disable the low-side driver to turn off the low-side switch. The
zero cross detector is disabled in FPWM mode.
For any peak current mode step-down converter, a compen-
sation ramp is needed to avoid subharmonic oscillations
when the duty cycle is higher than 50%. For the LM2630, this
compensation ramp is internally set to equal the maximum
down slope of the current amplifier output:
Wheren=5isthe gain of the current sense amplifier. The
maximum output voltage equals 6V. Also, a 10 H inductor
and a 0.025
sense resistor are assumed to determine the
internal compensation ramp. Different values of inductor and
sense resistor can be used as long as the resulted M
DOWN
(=nxR
SEN xVOUT/L) is less than MC.
PULSE-SKIPPING MODE AT LIGHT LOAD
Pulse-skipping mode can be enabled by pulling PFWM pin
low. This mode decreases switching frequency at light loads
to reduce the switching frequency related losses. If PFWM is
set at low, the controller goes into the pulse-skipping mode
when the sensed inductor current goes below the 25 mV
threshold set by the pulse-skipping comparator. In the pulse-
skipping mode, the high-side switch only turns on at the
beginning of a clock cycle when the voltage at the feedback
pin falls below the reference voltage. Once the switch is on,
it stays on until the sensed current rises to the 25 mV
threshold
FAST TRANSIENT RESPONSE
When the output voltage fails to exceed 97% of the nominal
level, the low voltage regulation(LREG) comparator will set
the PWM logic to turn the high-side switch on at maximum
duty cycle. This improves transient response since it by-
passes the error amplifier and PWM comparator. During
start-up, the LREG is disabled.
BOOST HIGH-SIDE GATE DRIVE
A flying capacitor is used to bootstrap the power supply for
the high-side driver as illustrated in
Figure 1. The boost
capacitor is charged from an internal voltage rail (about
5.5V) through an internal diode when the synchronous rec-
tifier (low-side MOSFET) is on, and then boosts up the
high-side gate voltage to turn high-side MOSFET on at the
beginning of next cycle. The internal diode connecting be-
tween the VIN pin and the CBOOT pin reduces the count of
external components. For low input voltage application (Vin
< 5V), some external charge pump circuitry can be used to
boost the gate voltage in order to reduce conduction loss.
Details will be discussed in the Application Circuits Section.
SUPPLY VOLTAGE FOR THE LM2630
When 5V is available, it is recommended to connect LM2630
V
IN (pin13) to 5V. This can improve efficiency (see the sec-
ond figure in Typical Performance Characteristics), and also
reduce power dissipation inside the IC. Since the 5V supply
is only used to power the LM2630 (including the gate charge
for the external MOSFETs), it only requires a small amount
of current.
REFERENCE
The 1.238V reference is of ±2.4% accuracy over tempera-
ture. A 220 pF capacitor is recommended between the V
REF
pin and ground. The load at the V
REF pin should not exceed
100A.
FREQUENCY CONTROL PIN (FADJ) AND SYNC PIN
With the FADJ pin open, the switching frequency is 200 kHz.
The frequency can be increased by connecting a resistor
between FADJ and ground. The device can also be synchro-
nized with an external CMOS or TTL logic clock in the range
from 200 kHz to 400 kHz. It is recommended to connect the
SYNC pin to ground if not used.
PROTECTIONS
The current limit comparator provides the cycle-by-cycle
current limit function by turning off the high-side MOSFET
whenever the sensed current reaches 110 mV. A second
level of current limit is accomplished by the 80% low voltage
detector: if the load pulls the output voltage down below 80%
of the nominal value, the device will turn off the high-side
MOSFET and turn on the low-side MOSFET in a latched
condition. This protection feature is disabled during startup.
The latched condition can be reset by shutting the device
down and then powering it up. Built-in input undervoltage
lockout circuit will keep most of the internal function blocks
off until the input voltage rises to about 3.5V.
SOFT START
A capacitor at the SS pin provides the soft start feature.
When the regulator is first powered up, or when the SD pin
goes high, a 10A current source charges up the SS capaci-
tor from the 0.6V clamping voltage. The switch duty cycle
starts with narrow pulses and gradually get wider as the SS
pin voltage ramps up to about 1.3V, above which the duty
cycle will be controlled by the maximum current limit until the
output voltage rises to the nominal value and the regulator
starts to operate in the normal current mode PWM control.
The LM2630 use a digital counter, referenced to the oscilla-
tor frequency, to set the soft start timeout. The timeout is
dependent on the switching frequency (timeout = 4096/F
S).
If the output voltage doesn’t move within the ±3% window of
the nominal value during this period, the device will latch
itself off.
POWER GOOD
The LM2630 provides a power good signal by monitoring the
voltage at the FB pin and compared the feedback voltage
with the V
REF voltage. Once the output voltage exceeds the
±9% window of the nominal value, the PGOOD pin goes low,
and stays low until the output voltage returns to the ±3%
window of the nominal value.
Design Procedure
Guidelines for selecting external components are discussed
in this section.
INDUCTOR SELECTION
The most critical parameters for the inductor are the induc-
tance, peak current and the dc resistance. The inductance is
related to the switching frequency and the ripple current:
LM2630
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