參數(shù)資料
型號: LM25011Q1MY
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, 2000 kHz SWITCHING FREQ-MAX, PDSO10
封裝: MSOP-10
文件頁數(shù): 8/20頁
文件大?。?/td> 458K
代理商: LM25011Q1MY
30094640
FIGURE 8. Option A – Lowest Cost Ripple Configuration
Option B) Intermediate Ripple Configuration:
This config-
uration generates less ripple at V
OUT than Option A above by
the addition of one capacitor (Cff), as shown in Figure 9.
30094641
FIGURE 9. Option B – Intermediate Ripple Configuration
Since the output ripple is passed by Cff to the FB pin with little
or no attenuation, R1’s value can be chosen so the minimum
ripple at V
OUT is 150 mVp-p. The minimum value for R1 is
calculated from:
where
ΔI is the minimum ripple current amplitude, which oc-
curs at minimum Vin. The minimum value for Cff is calculated
from:
where t
ON(max) is the maximum on-time (at minimum VIN), and
R
FB1//RFB2 is the parallel equivalent of the feedback resistors.
Option C) Minimum Ripple Configuration:
30094646
FIGURE 10. Option C: Minimum Output Ripple
Configuration
In some applications, the ripple induced by series resistor R1
may not be acceptable. An external ripple circuit, as shown in
Figure 10, can be used to provide the required ripple to the
FB pin.
1.
The time constant
τ=Rr*Cr should be greater than 8-10
times the switching period to generate a triangular ramp
at FB pin.
2.
The smallest ripple at feedback
ΔVFB = (VIN(min)-
VOUT)*TON(max)/
τ.
3.
The ramp capacitor Cr should much smaller than the ac
coupling capacitor Cac. Usually Cac=100nF, Cr=1nF,
and Rr is chosen to satisfy conditions 1 and 2 above.
PC BOARD LAYOUT
The LM25011 regulation and current limit comparators are
very fast, and respond to short duration noise pulses. Layout
considerations are therefore critical for optimum perfor-
mance. The layout must be as neat and compact as possible,
and all of the components must be as close as possible to
their associated pins. The two major current loops conduct
currents which switch very fast, and therefore those loops
must be as small as possible to minimize conducted and ra-
diated EMI. The first loop is formed by C
IN, through the VIN
to SW pins, L1, C
OUT, and back to CIN. The second current
loop is formed by R
S, D1, L1, COUT and back to RS. The
ground connection from CSG to the ground end of C
IN should
be as short and direct as possible.
The power dissipation within the LM25011 can be approxi-
mated by determining the circuit’s total conversion loss (P
IN -
P
OUT), and then subtracting the power losses in the free-
wheeling diode, the sense resistor, and the inductor. The
power loss in the diode is approximately:
P
D1 = IOUT x VF x (1-D)
where Iout is the load current, V
F is the diode’s forward volt-
age drop, and D is the on-time duty cycle. The power loss in
the sense resistor is:
P
RS = (IOUT)
2
x R
S x (1 – D)
The power loss in the inductor is approximately:
P
L1 = IOUT
2
x R
L x 1.1
where R
L is the inductor’s DC resistance, and the 1.1 factor
is an approximation for the AC losses. If it is expected that the
internal dissipation of the LM25011 will produce excessive
junction temperatures during normal operation, good use of
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LM25011/LM25011QLM25011A/LM25011AQ
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