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參數(shù)資料
| 型號： | LM2240N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Programmable Timer/Counter |
| 中文描述： | 1 TIMER(S), PROGRAMMABLE TIMER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 201K |
| 代理商： | LM2240N |
Functional Description
TL/H/10837–4
V
CC
e
Pin 16
GND
e
Pin 9
FIGURE 1. Logic Symbol
When power is applied to the LM2240 with no trigger or
reset inputs activated, the circuit starts with all outputs
HIGH. Application of a positive going trigger pulse to the
trigger pin initiates the timing cycle. The trigger input acti-
vates the time-base oscillator, enables the counter section
and sets the counter outputs LOW. The time-base oscillator
generates timing pulses with a period T
e
1 RC; this is the
period of the waveform appearing at pin 14. These clock
pulses are counted by the binary counter section. The tim-
ing sequence is completed when a positive going reset
pulse is applied to the Reset pin.
Once triggered, the circuit is immune from additional trigger
inputs until the timing cycle is completed or a reset input is
applied. If both the reset and trigger are activated simulta-
neously, the trigger takes precedence.
Figure 2 gives the timing sequence of output waveforms at
various circuit terminals, subsequent to a trigger input.
When the circuit is in a reset state, both the time-base and
the counter sections are disabled and all the counter out-
puts are HIGH.
TL/H/10837–5
FIGURE 2. Timing Diagram of Output Waveforms
In monostable applications, one or more of the counter out-
puts are connected to the reset terminal with S1 closed
(Figure 3). The circuit starts timing when a trigger is applied
and automatically resets itself to complete the timing cycle
when a programmed count is completed. Each of the vari-
ous multiplies of T shown at the LM2240’s outputs inFigure
3 represent the duration of time, after a trigger pulse, that
that particular output is low (it’s not the period of the wave-
form) if the output is not tied to any other outputs. T
O
repre-
sents the duration of time that the circuit output, which is the
common point of all the counter outputs which are shorted
together, is low. If none of the counter outputs are connect-
ed back to the reset terminal (switch S1 open), the circuit
operates in an astable or free running mode, following a
trigger input.
TL/H/10837–6
FIGURE 3. Basic Circuit Connection
for Timing Applications
(Monostable: S1 Closed; Astable: S1 Open)
Important Operating Information
Ground connection is pin 9.
Reset (R) (pin 10) sets all outputs HIGH.
Trigger (TRIG) (pin 11) sets all outputs LOW.
Time-base output (TBO) (pin 14) can be disabled by bring-
ing the RC input (pin 13) LOW via a 1.0 k
X
resistor.
Normal TBO (pin 14) is a negative going pulse greater than
500 ns.
NOTE: Under the conditions of high supply voltages (V
CC
l
7.0V) and low
values of timing capacitor (C
T
k
0.1
m
F), the pulse width of TBO
may be too narrow to trigger the counter section. This can be cor-
rected by connecting a 600 pF capacitor from TBO (pin 14) to
ground (pin 9).
Reset (pin 10) stops the time-base oscillator.
Outputs (O
0
. . . O
128
) (pins 1–8) sink 2.0 mA current with
V
OL
s
0.4V.
For use with external clock, minimum clock pulse amplitude
should be 3.0V, with greater than 1.0
m
s pulse duration.
5
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