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參數(shù)資料
| 型號： | LM1872 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Radio Control Receiver/Decoder |
| 中文描述： | 遙控接收器/解碼器 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 371K |
| 代理商： | LM1872 |
Circuit Description
(Continued)
and T3. This tank effectively keeps strong out-of-band sig-
nals such as FM and TV broadcast from cross-modulating
with the desired signal. When operating at 49 MHz or
72 MHz, CB interference is also effectively minimized. Im-
age rejection is relatively low, however, being only 7 dB
@
49 MHz, but this does not present a problem due to the
usual absence of strong interfering signals 910 kHz below
the desired signal.
The antenna signal is stepped down and DC coupled to the
mixer which consists of the emitter-coupled pair Q1 and Q2.
Emitter-follower, Q1, feeds the common-base device, Q2,
while effectively buffering the antenna from the LO energy
delivered by Q4. Mixer transconductance is 4 mmhos at low
frequency (1 MHz) falling to 3.3 mmhos at the upper end
(72 MHz).
The local oscillator utilizes an emitter coupled pair, Q3 and
Q4, for accurate control of mixer drive, I
1
. Quiescently, Q3
and Q4 share I
1
set by 0.69V/R5, but healthy voltage
swings at pin 2 due to oscillation of Q3 implement thorough
switching of the differential pair. As a result, the full 1.8 mA
of drive ‘‘tailgates’’ (switches) the mixer emitter coupled
pair, Q1 and Q2. This current is well regulated from supply
voltage changes by the V
BIAS
circuitry. The TC of V
BIAS
is
positive by design in order to impress a positive TC on I
1
so
as to compensate for the temperature dependence of bipo-
lar transconductance in the mixer. Inasmuch as Q4 oper-
ates as an emitter-gated, common-base-connected device,
excellent isolation between local oscillator and mixer is ob-
tained. As long as pin 4 is properly bypassed, Q5 presents a
low impedance to the base of Q4, resulting in low oscillator
noise. The oscillator easily operates up to 72 MHz with over-
tone crystals operating parallel mode.
The mixer signal is stepped down from the high Q mixer
tank, T1, and DC coupled to the IF via a secondary winding.
The IF stage consists of Q7, Q8 and Q10 and delivers a
transconductance of 4 mmhos
@
455 kHz. The quiescent
current, I
2
, is set at 120
m
A by V
BIAS
and a 6.2k resistor.
Again, the positive TC of V
BIAS
is used to compensate for
the temperature dependence of transconductance. The im-
pedance at the IF output, pin 15, is very high (
t
800k) per-
mitting the IF transformer, T2, to operate at near unloaded
Q (110). The overall 3 dB bandwidth of the receiver section
is 3.2 kHz (see characteristic curves); this is narrow enough
to permit adjacent channel operation without interference
yet wide enough to pass the 500
m
s modulation pulses (t
M
in Figure 2 ).
The IF signal is DC coupled to the digital detector which
consists of a high gain precision comparator, a 30
m
s inte-
grator, and a supply-referred 25 mV voltage reference.
Whenever the peak IF signal exceeds 25 mV, the compara-
tor drives Q11 to reset the digital envelope detector capaci-
tor, C12. Since it takes 30
m
s for the 1
m
A current source to
ramp C12 to the 3V (V
a
/2) necessary to fire the Schmitt
trigger, the presence of 455 kHz carrier (period
e
2.2
m
s)
greater than 25 mVp will prevent C12 from ever reaching
this threshold. When the carrier drops out, the Schmitt trig-
ger will respond 30
m
s later. This delay (like that associated
with the burst response of the 455 kHz IF tanks) is constant
over the time interval of interest. Thus, it is of no conse-
quence to timing accuracy because the LM1872 responds
only to negative edges in the decoder.
AGC is provided only to the IF; the mixer having sufficient
overload recovery for the magnitude of signals available
from a properly operating (i.e. good carrier ON/OFF ratio)
10,000
m
V/m transmitter. The AGC differential amplifier
regulates the peak carrier level to 100 mV by comparing it to
an internal 100 mV supply-referred voltage reference. The
resultant error signal is amplified and drives Q9 via rectifier
diode, D1, to shunt current away from Q10. C8 provides
compensation for the AGC loop which spans a 70 dB range.
The 100 mV AGC reference is accurately ratioed to the
25 mV detector reference to permit a controlled amount of
brief carrier loss before dropping below detector threshold.
Once into AGC, typically 60% amplitude modulation of the
PWM carrier is possible before the detector will recognize
the interference (see characteristic curves). This kind of
noise immunity is invaluable when the troublesome effects
of other physically close toys or walkie-talkies on the same
or adjacent frequencies are encountered.
DECODER SECTION
The purpose of the decoder is to extract the time informa-
tion from the carrier for the analog channels and the pulse
count information for the digital channels. The core of the
decoder is a three-stage binary counter chain comprising
flip-flops A, B, and C. The demodulated output from the de-
tector Schmitt-trigger drives both the counter chain and the
sync timer (Q12, R2, C6, and another Schmitt trigger). When
the RF carrier drops out for the first modulation pulse, t
M
,
the falling edge advances the counter (see Figure 2 ). Dur-
ing the t
M
interval the sync timer capacitor is held low by
Q12. When the carrier comes up again for the variable
channel interval, t
CH
, C6 begins to ramp towards threshold
(V
a
/2) but is unable to reach it in the short time that is
available. At the end of the t
CH
period the carrier drops out
again, the counter advances one more, and the sequence is
repeated for the second analog channel. To decode the two
analog channels, 3-input NAND gates G1 and G2 examine
the counter chain binary output so as to identify the time
slots that represent those channels. Decoded in this man-
ner, the output pulse width equals the sum of t
M
, a fixed
pulse, and t
CH
, a variable width pulse. A Darlington output
driver interfaces this repetitive pulse to standard hobby ser-
vos.
Following the transmission of the second analog channel, a
variable quantity from one to four, of fixed width pulses
(500
m
s) are transmitted that contain the digital channel in-
formation. Up until the end of the pulse group frame period,
t
F
, the decoder responds as if these fixed pulses were ana-
log channels but delivers no outputs. At the conclusion of
the frame the sync pulse, t
SYNC
, is sent. Since t
SYNC
is
always made longer than the sync timer period (t’
SYNC
e
3.5 ms), the sync timer will output a sync signal to the first of
two cascaded 10
m
s one-shots. The first one-shot enables
AND gates G3
G6 to read the A and B flip-flops of the
counter into a pair of RS latches. The state of flip-flop A, for
example, is then stored and buffered to drive 100 mA sink or
source at the channel A digital output. An identical parallel
path allows the state of flip-flop B to appear at the channel
B power output. Upon conclusion of the 10
m
s read pulse,
another 10
m
s one-shot is triggered that resets the counter
to be ready for the next frame.
8
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