參數(shù)資料
型號(hào)： LM1270NA
廠商： National Semiconductor Corporation
英文描述： Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing
中文描述： 高亮度場(chǎng)致200兆赫與I2C兼容的RGB視頻自動(dòng)上漿圖像增強(qiáng)
文件頁(yè)數(shù)： 20/27頁(yè)
文件大?。?/td> 1302K
代理商： LM1270NA
Register Descriptions
(Continued)
selected blank level, and to set the video output to black level to blank the video.
If bit 2 = 0, enable the analog circuits for normal operation (Default)
If bit 2 = 1, send the device into power save mode
Bit 3: Video Detect Enable: When this bit is set to 1, this enables the video detection logic and video detectors to run.
Default: 0
Bit 4: Set the output to the black level
If bit 4 = 0, normal video (Default)
If bit 4 = 1, video set to black level
Bit 5: Full IC reset: this is a self resetting bit. When a 1 is written to this bit, the IC is reset. The bit automatically returns to 0 after
reset has occurred.
If bit 5 = 0, normal (Default)
If bit 5 = 1, reset
Bit 6: Selects whether HFLYBACK or HSYNC is measured and used as the timing reference during video detect
If bit 6 = 0, HSYNC is selected (Default)
If bit 6 = 1, HFLYBACK is selected
Bit 7: Video detect reset: this is a self resetting bit. When a 1 is written to this bit, the video detect registers are reset to start a
new timing cycle. The bit automatically returns to 0 after reset has occurred.
If bit 7 = 0, normal (Default)
If bit 7 = 1, reset
Inputs and Outputs Controls—1
Register
I_O1
Addr
01
7
6
5
4
3
2
1
0
CL POL
CL I/O
BL POL
BLANK
VBL EN
RSV
VSY POL
HSY POL
Bit 0:
Selects the H sync input polarity
If bit 0 = 0, positive H sync input signal required. (Default)
If bit 0 = 1, negative H sync input signal required.
Selects the V sync input polarity
If bit 1 = 0, positive V sync input signal required. (Default)
If bit 1 = 1, negative V sync input signal required.
Reserved
Bit 3–4: Blanking operation:
Bit 1:
Bit 2:
BIT4
0
0
1
BIT3
0
1
X
BLANK/INTERRUPT OUTPUT PIN
No blank signal
Vertical Blanking only (Default)
Blank
Bit 5:
Selects the BLANK or INTERRUPT signal output polarity
If bit 4 = 0, positive active. (Default)
If bit 4 = 1, negative active
Determines whether the CLAMP pin is an input or output
If bit 6 = 0, input (Default)
If bit 6 = 1, output
Selects the CLAMP output or input active level polarity
If bit 7 = 0, positive active. (Default)
If bit 7 = 1, negative active
Bit 6:
Bit 7:
Clamp Position
Register
CL_POS0
CL_POS1
Addr
02
03
7
6
5
4
3
2
1
0
CLP7
CLP6
CLP5
CLP4
CLP3
CLP2
CLP1
CLP9
CLP0
CLP8
This is a 10 bit wide register that sets the position of the clamp pulse with respect to the leading edge of the H sync pulse in
increments of 2 cycles of the main PLL pixel clock.
L
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