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參數(shù)資料
| 型號(hào)： | LM122H-MIL |
| 英文描述： | Analog Timer Circuit |
| 中文描述： | 模擬定時(shí)器電路 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 281K |
| 代理商： | LM122H-MIL |
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Application Hints
(Continued)
Triggering with Negative Edge
Although the LM122 is triggered by a positive going trigger
signal, a differentiator tied to a normally ‘‘high’’ trigger will
result in negative edge triggering. In Figure 19, R1 serves
the dual purpose of holding the trigger pin normally high and
differentiating the input trigger pulse coupled through C1.
The timing diagram included with Figure 21 shows that trig-
gering actually occurs a short time after the negative going
trigger, while positive going triggers have no effect. The de-
lay time between a negative trigger signal and actual starts
of timing is approximately (0.5 to 1.5) (R1
#
C1) depending
on the trigger amplitude, or about 2.5 to 7.5
m
s with the
values shown. This time will have to be increased for C
t
larger than 0.01
m
F because C
t
is charged to V
REF
whenev-
er the trigger pin is kept high and must reset itself during the
short time that the trigger pin voltage is low. A conservative
value for C1 is:
C1
t
C
t
10
Chain of Timers
The LM122 can be connected as a chain of timers quite
easily with no interface required. InFigure 20A and20B, two
TL/H/7768–30
FIGURE 19. Timer Triggered by Negative
Edge of Input Pulse
possible connections are shown. In both cases, the output
of the timer is low during the timing period so that the posi-
tive going signal at the end of the timing period can trigger
the next timer. There is no limitation on the timing period of
one timer with respect to any other timer before or after it,
because the trigger input to any timer can be high or low
when that timer ends its timing period.
TL/H/7768–31
(a)
TL/H/7768–32
TL/H/7768–33
(b)
FIGURE 20. Chain of Timers
12
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