參數(shù)資料
型號(hào)： LM1229VEC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 運(yùn)動(dòng)控制電子
英文描述： I2C Compatible CMOS TV RGB and Deflection Processor
中文描述： WAVEFORM GENERATION, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 23/27頁(yè)
文件大小： 969K
代理商： LM1229VEC
Application Register Detail
(Continued)
HORIZONTAL EHT CORRECTION
Register
HEHT
Addr
0x42
Bit 7
EQPRM
Bit 6
XRayOff
Bit 5
HOff
Bit 4
HPCOff
Bit 3
EHTEN
Bit 2
POL
Bit 1
Bit 0
HEHT[3:0]
Bit 7:
When this bit is a 0, no attempt is made to remove HSYNC equalizing pulses. When set to a 1, HSYNC equalizing
pulses are removed.
When this bit is a 0, the XRay protection is functional. When set to a 1, the XRay protection is disabled.
When set to a 1, HDRIVE output is off and the output will be pulled high by the external pullup resistor (this is the power
up default). When this bit is a 0, the HDRIVE output is functional.
When this bit is a 0, the horizontal phase corrections (parallelogram and bow) are functional. When set to a 1, these
corrections are disabled.
When this bit is 0 the HEHT compensation is enabled. When a 1, compensation is disabled.
This is the compensation polarity bit. When it is a 0, a reduction in the voltage at pin 20 causes the picture to shift to
the left. When it is a 1, the shift is to the right.
Bits 1–0: These two bits determine the amplitude of the phase correction. When both are both 0, the compensation is a minimum
(not zero) and is determined by the external resistor R
connected between pins 21 and 24. When these bits are 01
through 11, the compensation is increased according to
Table 4
.
PARALLELOGRAM CORRECTION
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Register
PAR
Addr
0x43
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAR[7:0]
Bits 7–0: Sets the parallelogram correction which can be either polarity. A value of 0x7F gives no correction. A value of 0x00 tilts
the picture to the right and 0xFF tilts the picture to the left.
PINCUSHION BALANCE (BOW)
Register
PIN_BAL
Addr
0x44
Bit 7
Bit 6
Bit 5
Bit 4
PIN_BAL[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bits 7–0: Sets the amount of pin balance (bow) correction which can be either polarity. A value of 0x7F gives no correction. A
value of 0x00 bows the top and bottom to the left. A value of 0xFF bows the top and bottom to the right.
VERTICAL SIZE
Register
VSIZE
Addr
0x45
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VSIZE[7:0]
Bits 7–0: Sets the amplitude of the vertical ramp. 0x00 gives minimum size and 0xFF gives maximum size.
VERTICAL EHT CORRECTION
Register
VEHT
Addr
0x46
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VEHT2[7:4]
VEHT1[3:0]
Bits 7–4: Sets the amount of EW EHT correction. This can be disabled with bit 4 of the SYNCPOL register.
Bits 4–0: Sets the amount of vertical drive EHT correction. This can be disabled with bit 3 of the SYNCPOL register.
‘C’ CORRECTION
Register
C
Addr
0x47
Bit 7
X
Bit 6
Bit 5
Bit 4
Bit 3
C[6:0]
Bit 2
Bit 1
Bit 0
Bits 6–0: Sets the amount of C correction which can be either polarity. A value of 0x3F gives no correction. Smaller values will
stretch the lower part of the screen. Larger values will stretch the upper part of the screen.
‘S’ CORRECTION
Register
S
Addr
0x48
Bit 7
X
Bit 6
Bit 5
Bit 4
Bit 3
S[6:0]
Bit 2
Bit 1
Bit 0
Bits 6–0: Sets the amount of S correction. 0x00 gives no correction and 0x7F gives maximum correction.
VERTICAL POSITION
Register
VPOS
Addr
0x49
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VPOS[7:0]
L
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