參數(shù)資料
    型號(hào): LK1301-9EPDDB1
    元件分類: 電源模塊
    英文描述: 1-OUTPUT 150 W AC-DC REG PWR SUPPLY MODULE
    封裝: METAL, CASE K02, MODULE
    文件頁數(shù): 15/26頁
    文件大?。?/td> 601K
    代理商: LK1301-9EPDDB1
    Cassette Style
    150 Watt AC-DC Converters
    K Series
    Edition 01/01.2001
    22/26
    Vo1+
    Vo1–
    D
    UD
    ID
    Rp
    Input
    11007
    NPN output (D5...DD):
    Connector pin D is internally connected via the collector-
    emitter path of a NPN transistor to the negative potential of
    output 1.
    UD
    < 0.4 V (logic low) corresponds to a monitored
    voltage level (
    Ui and/or Uo1)
    > U
    t + Uh. The current ID
    through the open collector should not exceed 20 mA. The
    NPN output is not protected against external overvoltages.
    UD should not exceed 40 V.
    Ui, Uo1 status
    D output,
    UD
    Ui or Uo1 < Ut
    high, H,
    ID ≤ 25 A at UD = 40 V
    Ui and Uo1 > Ut + Uh
    low, L,
    UD ≤ 0.4 V at ID = 20 mA
    Vo1+
    Vo1–
    D
    UD
    ID
    Rp
    Input
    11006
    Fig. 33
    Option D0...D4: JFET output, ID
    ≤ 2.5 mA
    JFET output (D0…D4):
    Connector pin D is internally connected via the drain-
    source path of a JFET (self-conducting type) to the negative
    potential of output 1.
    UD
    ≤ 0.4 V (logic low) corresponds to a
    monitored voltage level (
    Ui and/or Uo1)
    <U
    t. The current ID
    through the JFET should not exceed 2.5 mA. The JFET is
    protected by a 0.5 W Zener diode of 8.2 V against external
    overvoltages.
    Ui, Uo1 status
    D output,
    UD
    Ui or Uo1 < Ut
    low, L,
    UD ≤ 0.4 V at ID = 2.5 mA
    Ui and Uo1 > Ut + Uh
    high, H,
    ID ≤ 25 A at UD = 5.25 V
    Fig. 34
    Option D5...DD: NPN output, Uo1
    ≤ 40 V, I
    D
    ≤ 20 mA
    Threshold tolerances and hysteresis:
    If
    Ui is monitored, the internal input voltage after the input
    filter and rectifier is measured. Consequently this voltage
    differs from the voltage at the connector pins by the voltage
    drop
    U
    ti across input filter and rectifier. The threshold lev-
    els of the D0 and D9 options are factory adjusted at nomi-
    nal output current
    Io nom and at TA = 25°C. The value of Uti
    depends upon the threshold level
    Ut, temperature and input
    current. The input current is a function of the input voltage
    and the output power.
    Fig. 35
    Definition of Uti, DUti and DUhi (JFET output)
    Table 19: D-output logic signals
    Version of D
    Ui < Ut resp. Uo < Ut
    Ui > Ut + Uh resp. Uo > Ut
    Configuration
    D1, D2, D3, D4, D0
    low
    high
    JFET
    D5, D6, D7, D8, D9, DD
    high
    low
    NPN
    DUti
    Uhi
    UD low
    UD
    UD high
    Ui
    P
    o
    =
    P
    o
    nom
    P
    o
    =
    0
    P
    o
    =
    0
    Uti
    P
    o
    =
    P
    o
    nom
    11021
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