參數(shù)資料
型號(hào)： LIS3LV02DQ-TR
廠商： 意法半導(dǎo)體
英文描述： MEMS INERTIAL SENSOR 3-Axis - +-2g/+-6g Digital Output Low Voltage Linear Accelerometer
中文描述： MEMS慣性傳感器3軸- - 2克/ - 6g的數(shù)字輸出低電壓線性加速度計(jì)
文件頁數(shù)： 18/42頁
文件大?。?/td> 379K
代理商： LIS3LV02DQ-TR
5 Digital Interfaces
LIS3LV02DQ
18/42
CD00047926
5.1.1
I
2
C Operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this
has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and the
eighth bit tells whether the Master is receiving data from the slave or transmitting data to the
slave. When an address is sent, each device in the system compares the first seven bits after a
start condition with its address. If they match, the device considers itself addressed by the
Master. The Slave ADdress (SAD) associated to the LIS3LV02DQ is 0011101b.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during
the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable
low during the HIGH period of the acknowledge clock pulse. A receiver which has been
addressed is obliged to generate an acknowledge after each byte of data has been received.
The I
2
C embedded inside the LIS3LV02DQ behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a salve address is sent, once a slave
acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb
represent the actual register address while the MSB enables address auto increment. If the
MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow
multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the Master will transmit to the slave with direction unchanged.
Transfer when Master is writing one byte to slave
Transfer when Master is writing multiple bytes to slave:
Transfer when Master is receiving (reading) one byte of data from slave:
Transfer when Master is receiving (reading) multiple bytes of data from slave
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of
bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb)
first. If a receiver can’t receive another complete byte of data until it has performed some other
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
SAK
SAK
Master
ST
SAD + W
SUB
DATA
DATA
SP
Slave
SAK
SAK
SAK
SAK
Master
ST
SAD + W
SUB
SR
SAD + R
NMAK
SP
Slave
SAK
SAK
SAK
DATA
Master
ST
SAD + W
SUB
SR
SAD + R
MAK
Slave
SAK
SAK
SAK
DATA
Master
MAK
NMAK
SP
Slave
DATA
DATA
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