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參數(shù)資料
| 型號(hào)： | LH5481 |
| 廠商： | Sharp Corporation |
| 英文描述： | Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO |
| 中文描述： | 級(jí)聯(lián)64 × 8的FIFO級(jí)聯(lián)64 × 9先進(jìn)先出 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | LH5481 |
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OPERATIONAL DESCRIPTION
Unlike earlier versions of FIFOs, the LH5481 and
LH5491 use dual-port Random-Access-Memory, write
and read pointers, and special control logic. The write
pointer is incremented by the falling edge of the Shift In
(SI) signal, while the read pointer is incremented by the
falling edge of the Shift Out (SO) signal. The Input Ready
(IR) signal enables data writing to the FIFO. The Output
Ready (OR) signal indicates valid read information is
available on the Data Output (DO) pins.
Resetting The FIFO
The FIFO must be reset, upon power-up, using the
Master Reset (MR) signal. This causes the FIFO to enter
an empty state, indicated by the Output Ready (OR) being
LOW and Input Ready (IR) being HIGH. All Data Output
(DO) pins will be LOW in this state. The AFE flag will be
HIGH, and the HF flag will be LOW.
If Shift In (SI) is HIGH, when the Master Reset (MR)
signal is ended, then the data on the Data Input (DI) pins
will be written into the FIFO, and Input Ready (IR) will
return LOW until Shift In (SI) is brought LOW.
If Shift In (SI) is LOW when the Master Reset (MR) is
deasserted, then Input Ready (IR) goes HIGH, but the
data on the Data Input (DI) pins does not enter the FIFO
until Shift In (SI) goes HIGH.
Shifting Data In
Data Input (DI) is shifted into the FIFO on the rising
edge of Shift In (SI). This loads input data into the FIFO,
and causes Input Ready (IR) to go LOW. When a falling
edge of Shift In (SI) occurs,the write pointer increments
to the next word position, and Input Ready (IR) goes
HIGH, indicating that the FIFO is ready to accept new
data. When the FIFO is full, Input Ready (IR) remains
LOW after the negative edge of Shift In (SI) signal; Shift
Out (SO) action is required to unload a word of data and
bring Input Ready (IR) HIGH. (See ‘Bubblethrough Con-
dition’ description.)
Shifting Data Out
Data is shifted out of the FIFO on the falling edge of
Shift Out (SO). The read pointer increments to the next
word location; FIFO data, if present, appears on the Data
Output (DO) pins; and the Output Ready (OR) signal goes
HIGH. If FIFO data is not present, Output Ready (OR)
stays LOW, indicating that the FIFO is empty; in this case,
the last valid data read from the FIFO remains on the Data
Output (DO) pins. When the FIFO is not empty, Output
Ready (OR) goes LOW after the rising edge of Shift Out
(SO). The previous data remains on the Data Output (DO)
pins until a falling edge of Shift Out (SO).
Fallthrough Condition
When the FIFO is empty, a data word entering through
the Shift In (SI) action follows one of two sequences.
If Shift Out (SO) is LOW, the data propagates to the
Data Output (DO) pins; and Output Ready (OR) goes
HIGH and stays HIGH until the next rising edge of Shift
Out (SO).
If Shift Out (SO) is held HIGH while data is shifted into
an empty FIFO as occurs in depth cascading of FIFOs,
data propagates to the Data Output (DO) pins, and Output
Ready (OR) pulses HIGH for a minimum time duration
specified by t
POR
and then goes back LOW again. The
stored word remains on the Data Output (DO) pins. If
more words are written into the FIFO, they line up behind
the first word, and do not appear on the Data Output (DO)
pins until Shift Out (SO) has returned LOW.
Bubblethrough Condition
When the FIFO is full, Shift Out (SO) action initiates
one of the following two sequences:
If Shift In (SI) is LOW, Input Ready (IR) goes HIGH and
stays HIGH until the next rising edge of Shift In (SI).
If Shift In (SI) is held HIGH while data is shifted out of
a full FIFO, as occurs in depth cascading of FIFOs, Input
Ready (IR) pulses HIGH for a minimum time duration
specified by t
PIR
, and then goes back LOW again. Special
Data Input (DI) setup and hold times (t
SIR
and t
HIR
,
respectively) are defined for this condition.
LH5481/91
64
×
8 / 64
×
9 FIFO
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH5493 | 4K x 9 Parallel-to Serial FIFO |
| LH5496-50 | CMOS 512 X 9 FIFO |
| LH5496-65 | CMOS 512 X 9 FIFO |
| LH5496-80 | CMOS 512 X 9 FIFO |
| LH5496D-15 | CMOS 512 X 9 FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH5481D-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Asynchronous FIFO |
| LH5481D-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Asynchronous FIFO |
| LH5481D-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Asynchronous FIFO |
| LH5481U-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Asynchronous FIFO |
| LH5481U-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Asynchronous FIFO |
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