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參數(shù)資料
| 型號(hào)： | LH52258A |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 32K x 8 Static RAM |
| 中文描述： | 32K的× 8的CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | LH52258A |
TIMING DIAGRAMS – WRITE CYCLE
Addresses must be stable during Write cycles. The
outputs will remain in the High-Z state if W is LOW when
E goes LOW. If G is HIGH, the outputs will remain in the
High-Z state. Although these examples illustrate timing
with G active, it is recommended that G be held HIGH for
all Write cycles. This will prevent the LH52258A’s outputs
from becoming active, preventing bus contention, thereby
reducing system noise.
Write Cycle No. 1 (W Controlled)
Chip is selected: E is LOW, G is LOW. Using only W
to control Write cycles may not offer the best performance
since both t
WHZ
and t
DW
timing specifications must be
met.
Write Cycle No. 2 (E Controlled)
G is LOW. DQ lines may transition to Low-Z if the falling
edge of W occurs after the falling edge of E.
t
WC
VALID ADDRESS
ADDRESS
52258A-7
t
AW
t
AH
t
WP
t
AS
t
WHZ
t
WLZ
t
DH
HIGH-Z
W
DQ
DATA ON
DQ LINES
PREVIOUS OUTPUT
INPUT
t
DW
LOW-Z
Figure 7. Write Cycle No. 1
t
WC
VALID ADDRESS
ADDRESS
52258A-8
W
E
DQ
t
WP
t
EW
t
AH
t
DW
t
DH
t
ELZ
t
AS
DATA ON
DQ LINES
HIGH-Z
LOW-Z
HIGH-Z
INPUT
t
WHZ
Figure 8. Write Cycle No. 2
CMOS 32K
×
8 Static RAM
LH52258A
7
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| LH525C2T | 256K SRAM |
| LH525C9N | 256K SRAM |
| LH525CL2 | 256K SRAM |
| LH525CL9 | 256K SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH52258AD-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LH52258AD-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LH52258AD-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LH52258AD-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LH52258AK-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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