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參數(shù)資料
| 型號： | LFXP3E-3T144I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 83/397頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.1KLUTS 100I/O 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XP |
| 邏輯元件/單元數(shù)： | 3000 |
| RAM 位總計(jì)： | 55296 |
| 輸入/輸出數(shù)： | 100 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
9-8
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
The various ports and their definitions for the Single Port Memory are included in Table 9-1. The table lists the cor-
responding ports for the module generated by IPexpress and for the EBR RAM_DQ primitive.
Table 9-1. EBR-based Single Port Memory Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal forms the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-bit
bus, so it can easily cascade eight memories. If the memory size specified by the user requires more than eight
EBR blocks, the software automatically generates the additional address decoding logic which is implemented in
the PFU (external to the EBR blocks).
Each EBR block consists of 9,216 bits of RAM. The values for x (for Address) and y (Data) for each EBR block for
the devices are included in Table 9-2.
Table 9-2. Single Port Memory Sizes for 9K Memories for LatticeECP/EC Devices
Table 9-3 shows the various attributes available for the Single Port Memory (RAM_DQ). Some of these attributes
are user selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Table 9-3. Single Port RAM Attributes for LatticeECP/EC Devices
Port Name in
Generated Module
Port Name in the
EBR Block Primitive
Description
Active State
Clock
CLK
Clock
Rising Clock Edge
ClockEn
CE
Clock Enable
Active High
Address
AD[x:0]
Address Bus
—
Data
DI[y:0]
Data In
—
Q
DO[y:0]
Data Out
—
WE
Write Enable
Active High
Reset
RST
Reset
Active High
—
CS[2:0]
Chip Select
—
Single Port
Memory Size
Input Data
Output Data
Address [MSB:LSB]
8K x 1
DI
DO
AD[12:0]
4K x 2
DI[1:0]
DO[1:0]
AD[11:0]
2K x 4
DI[3:0]
DO[3:0]
AD[10:0]
1K x 9
DI[8:0]
DO[8:0]
AD[9:0]
512 x 18
DI[17:0]
DO[17:0]
AD[8:0]
256 x 36
DI[35:0]
DO[35:0]
AD[7:0]
Attribute
Description
Values
Default Value
User Selectable
Through
IPexpress
DATA_WIDTH
Data Word Width
1, 2, 4, 9, 18, 36
1
YES
REGMODE
Register Mode (Pipelining) NOREG, OUTREG
NOREG
YES
RESETMODE
Selects the Reset type
ASYNC, SYNC
ASYNC
YES
CSDECODE
Chip Select Decode
000, 001, 010, 011, 100, 101, 110,
111
000
NO
WRITEMODE
Read / Write Mode
NORMAL, WRITETHROUGH,
READBEFOREWRITE
NORMAL
YES
GSR
Global Set Reset
ENABLED, DISABLED
ENABLED
YES
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| LFXP3E-3TN100C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 62 IO 1.2V -3 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP3E-3TN100I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 62 IO 1.2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP3E-3TN144C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 100 IO 1.2 V -3 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP3E-3TN144I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 100 IO 1.2 V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP3E-4Q208C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 136 IO 1.2 V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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