
9-19
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-20. True Dual Port RAM Timing Waveform – READ BEFORE WRITE Mode, with Output Registers
Add_A0
Add_A1
Add_A2
New
Data_A0
New
Data_A1
Invalid Data
New_Data_A0
ClockA
WrEnA
AddressA
DataA
QA
ClockEnA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
tSUDATA_EBR
tHDATA_EBR
t
SUCE_EBR
tHCE_EBR
tCOO_EBR
Old_Data_A1
Old_Data_A0
New
Data_A1
Add_B0
Add_B1
Add_B2
New
Data_B0
New
Data_B1
Invalid Data
New_Data_B0
ClockB
WrEnB
AddressB
DataB
QB
ClockEnB
tSUWREN_EBR
t
HWREN_EBR
tSUADDR_EBR
tHADDR_EBR
tSUDATA_EBR
tHDATA_EBR
tSUCE_EBR
tHCE_EBR
tCOO_EBR
Old_Data_B1
Old_Data_B0
New
Data_B1