
9-20
Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-21. True Dual Port RAM Timing Waveform – WRITE THROUGH Mode, without Output Registers
Add_A0
Add_A1
Add_A0
Data_A0
Data_A1
Data_A2
Data_A3
Data_A4
Invalid Data
Data_A1
ClockA
WrEnA
AddressA
DataA
QA
ClockEnA
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
t SUDATA_EBR
t HDATA_EBR
tSUCE_EBR
tHCE_EBR
tCO_EBR
Data_A2
Data_A0
Data_A3
Data_A4
Add_B0
Add_B1
Add_B0
Data_B0
Data_B1
Data_B2
Data_B3
Data_B4
Invalid Data
Data_B1
ClockB
WrEnB
AddressB
DataB
QB
ClockEnB
tSUWREN_EBR
tHWREN_EBR
tSUADDR_EBR
tHADDR_EBR
tSUDATA_EBR
tHDATA_EBR
tSUCE_EBR
tHCE_EBR
tCO_EBR
Data_B2
Data_B0
Data_B3
Data_B4