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3-7
DC and Switching Characteristics
Lattice Semiconductor
LatticeXP Family Data Sheet
sysIO Recommended Operating Conditions
VCCIO
VREF (V)
Standard
Min.
Typ.
Max.
Min.
Typ.
Max.
LVCMOS 3.3
3.135
3.3
3.465
—
LVCMOS 2.5
2.375
2.5
2.625
—
LVCMOS 1.8
1.71
1.8
1.89
—
LVCMOS 1.5
1.425
1.5
1.575
—
LVCMOS 1.2
1.14
1.2
1.26
—
LVTTL
3.135
3.3
3.465
—
PCI33
3.135
3.3
3.465
—
SSTL18 Class I
1.71
1.8
1.89
0.833
0.9
0.969
SSTL2 Class I, II
2.375
2.5
2.625
1.15
1.25
1.35
SSTL3 Class I, II
3.135
3.3
3.465
1.3
1.5
1.7
HSTL15 Class I
1.425
1.5
1.575
0.68
0.75
0.9
HSTL15 Class III
1.425
1.5
1.575
—
0.9
—
HSTL 18 Class I, II
1.71
1.8
1.89
—
0.9
—
HSTL 18 Class III
1.71
1.8
1.89
—
1.08
—
LVDS
2.375
2.5
2.625
—
LVPECL
1
3.135
3.3
3.465
—
BLVDS
1
2.375
2.5
2.625
—
1. Inputs on chip. Outputs are implemented with the addition of external resistors.