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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LFXP20C-3F256I
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 332/397闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 19.7KLUTS 188I/O 256-BGA
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绯诲垪锛� XP
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 20000
RAM 浣嶇附瑷堬細 405504
杓稿叆/杓稿嚭鏁�(sh霉)锛� 188
闆绘簮闆诲锛� 1.71 V ~ 3.465 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
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渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
3
VCCAUX (3.3V) ........................................................................................................................................... 8-3
VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-3
Input Reference Voltage (VREF1, VREF2)................................................................................................... 8-3
VREF1 for DDR Memory Interface ............................................................................................................. 8-3
Mixed Voltage Support in a Bank.............................................................................................................. 8-4
sysIO Standards Supported in Each Bank......................................................................................................... 8-5
LVCMOS Buffer Configurations ......................................................................................................................... 8-5
Programmable Pull-up/Pull-Down/Buskeeper........................................................................................... 8-5
Programmable Drive ................................................................................................................................. 8-5
Programmable Slew Rate ......................................................................................................................... 8-7
Open Drain Control ................................................................................................................................... 8-7
Differential SSTL and HSTL Support ................................................................................................................. 8-7
PCI Support with Programmable PCICLAMP .................................................................................................... 8-7
5V Interface with PCI Clamp Diode.................................................................................................................... 8-8
Programmable Input Delay ................................................................................................................................ 8-9
Software sysIO Attributes................................................................................................................................... 8-9
IO_TYPE ................................................................................................................................................... 8-9
OPENDRAIN........................................................................................................................................... 8-10
DRIVE ..................................................................................................................................................... 8-10
PULLMODE ............................................................................................................................................ 8-11
PCICLAMP.............................................................................................................................................. 8-11
SLEWRATE ............................................................................................................................................ 8-11
FIXEDDELAY.......................................................................................................................................... 8-11
DIN/DOUT............................................................................................................................................... 8-11
LOC......................................................................................................................................................... 8-12
Design Considerations and Usage................................................................................................................... 8-12
Banking Rules ......................................................................................................................................... 8-12
Differential I/O Rules ............................................................................................................................... 8-12
Assigning VREF/ VREF Groups for Referenced Inputs............................................................................. 8-12
Differential I/O Implementation......................................................................................................................... 8-13
LVDS....................................................................................................................................................... 8-13
BLVDS .................................................................................................................................................... 8-13
RSDS ...................................................................................................................................................... 8-13
LVPECL .................................................................................................................................................. 8-13
Differential SSTL and HSTL.................................................................................................................... 8-13
Technical Support Assistance.......................................................................................................................... 8-13
Appendix A. HDL Attributes for Synplify
and Precision RTL Synthesis ........................................................ 8-15
VHDL Synplify/Precision RTL Synthesis.......................................................................................................... 8-15
Syntax ..................................................................................................................................................... 8-15
Examples ................................................................................................................................................ 8-15
Verilog for Synplify ........................................................................................................................................... 8-18
Syntax ..................................................................................................................................................... 8-18
Examples ................................................................................................................................................ 8-18
Verilog for Precision RTL Synthesis................................................................................................................. 8-20
Syntax ..................................................................................................................................................... 8-20
Example .................................................................................................................................................. 8-20
Appendix B. sysIO Attributes Using Preference Editor User Interface.............................................................8-22
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-23
IOBUF ..................................................................................................................................................... 8-23
LOCATE.................................................................................................................................................. 8-23
USE DIN CELL........................................................................................................................................ 8-24
USE DOUT CELL.................................................................................................................................... 8-24
PGROUP VREF ...................................................................................................................................... 8-24
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PDF鎻忚堪
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AS1359-BTTT-45 IC REG LDO 4.5V .3A TSOT23-5
MIC2211-GSYML TR IC REG LDO 1.8V/3.3V 10-MLF
AS1359-BTTT-27 IC REG LDO 2.7V .3A TSOT23-5
HSC40DRYS-S734 CONN EDGECARD 80POS DIP .100 SLD
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