- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗4570 > LFXP20C-3F256I (Lattice Semiconductor Corporation)IC FPGA 19.7KLUTS 188I/O 256-BGA PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LFXP20C-3F256I |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 332/397闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 19.7KLUTS 188I/O 256-BGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | XP |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 20000 |
| RAM 浣嶇附瑷堬細 | 405504 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 188 |
| 闆绘簮闆诲锛� | 1.71 V ~ 3.465 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 100°C |
| 灏佽/澶栨锛� | 256-BGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FPBGA锛�17x17锛� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�绗�221闋�绗�222闋�绗�223闋�绗�224闋�绗�225闋�绗�226闋�绗�227闋�绗�228闋�绗�229闋�绗�230闋�绗�231闋�绗�232闋�绗�233闋�绗�234闋�绗�235闋�绗�236闋�绗�237闋�绗�238闋�绗�239闋�绗�240闋�绗�241闋�绗�242闋�绗�243闋�绗�244闋�绗�245闋�绗�246闋�绗�247闋�绗�248闋�绗�249闋�绗�250闋�绗�251闋�绗�252闋�绗�253闋�绗�254闋�绗�255闋�绗�256闋�绗�257闋�绗�258闋�绗�259闋�绗�260闋�绗�261闋�绗�262闋�绗�263闋�绗�264闋�绗�265闋�绗�266闋�绗�267闋�绗�268闋�绗�269闋�绗�270闋�绗�271闋�绗�272闋�绗�273闋�绗�274闋�绗�275闋�绗�276闋�绗�277闋�绗�278闋�绗�279闋�绗�280闋�绗�281闋�绗�282闋�绗�283闋�绗�284闋�绗�285闋�绗�286闋�绗�287闋�绗�288闋�绗�289闋�绗�290闋�绗�291闋�绗�292闋�绗�293闋�绗�294闋�绗�295闋�绗�296闋�绗�297闋�绗�298闋�绗�299闋�绗�300闋�绗�301闋�绗�302闋�绗�303闋�绗�304闋�绗�305闋�绗�306闋�绗�307闋�绗�308闋�绗�309闋�绗�310闋�绗�311闋�绗�312闋�绗�313闋�绗�314闋�绗�315闋�绗�316闋�绗�317闋�绗�318闋�绗�319闋�绗�320闋�绗�321闋�绗�322闋�绗�323闋�绗�324闋�绗�325闋�绗�326闋�绗�327闋�绗�328闋�绗�329闋�绗�330闋�绗�331闋�鐣�(d膩ng)鍓嶇332闋�绗�333闋�绗�334闋�绗�335闋�绗�336闋�绗�337闋�绗�338闋�绗�339闋�绗�340闋�绗�341闋�绗�342闋�绗�343闋�绗�344闋�绗�345闋�绗�346闋�绗�347闋�绗�348闋�绗�349闋�绗�350闋�绗�351闋�绗�352闋�绗�353闋�绗�354闋�绗�355闋�绗�356闋�绗�357闋�绗�358闋�绗�359闋�绗�360闋�绗�361闋�绗�362闋�绗�363闋�绗�364闋�绗�365闋�绗�366闋�绗�367闋�绗�368闋�绗�369闋�绗�370闋�绗�371闋�绗�372闋�绗�373闋�绗�374闋�绗�375闋�绗�376闋�绗�377闋�绗�378闋�绗�379闋�绗�380闋�绗�381闋�绗�382闋�绗�383闋�绗�384闋�绗�385闋�绗�386闋�绗�387闋�绗�388闋�绗�389闋�绗�390闋�绗�391闋�绗�392闋�绗�393闋�绗�394闋�绗�395闋�绗�396闋�绗�397闋�
Table of Contents
Lattice Semiconductor
LatticeXP Family Handbook
3
VCCAUX (3.3V) ........................................................................................................................................... 8-3
VCCJ (1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-3
Input Reference Voltage (VREF1, VREF2)................................................................................................... 8-3
VREF1 for DDR Memory Interface ............................................................................................................. 8-3
Mixed Voltage Support in a Bank.............................................................................................................. 8-4
sysIO Standards Supported in Each Bank......................................................................................................... 8-5
LVCMOS Buffer Configurations ......................................................................................................................... 8-5
Programmable Pull-up/Pull-Down/Buskeeper........................................................................................... 8-5
Programmable Drive ................................................................................................................................. 8-5
Programmable Slew Rate ......................................................................................................................... 8-7
Open Drain Control ................................................................................................................................... 8-7
Differential SSTL and HSTL Support ................................................................................................................. 8-7
PCI Support with Programmable PCICLAMP .................................................................................................... 8-7
5V Interface with PCI Clamp Diode.................................................................................................................... 8-8
Programmable Input Delay ................................................................................................................................ 8-9
Software sysIO Attributes................................................................................................................................... 8-9
IO_TYPE ................................................................................................................................................... 8-9
OPENDRAIN........................................................................................................................................... 8-10
DRIVE ..................................................................................................................................................... 8-10
PULLMODE ............................................................................................................................................ 8-11
PCICLAMP.............................................................................................................................................. 8-11
SLEWRATE ............................................................................................................................................ 8-11
FIXEDDELAY.......................................................................................................................................... 8-11
DIN/DOUT............................................................................................................................................... 8-11
LOC......................................................................................................................................................... 8-12
Design Considerations and Usage................................................................................................................... 8-12
Banking Rules ......................................................................................................................................... 8-12
Differential I/O Rules ............................................................................................................................... 8-12
Assigning VREF/ VREF Groups for Referenced Inputs............................................................................. 8-12
Differential I/O Implementation......................................................................................................................... 8-13
LVDS....................................................................................................................................................... 8-13
BLVDS .................................................................................................................................................... 8-13
RSDS ...................................................................................................................................................... 8-13
LVPECL .................................................................................................................................................. 8-13
Differential SSTL and HSTL.................................................................................................................... 8-13
Technical Support Assistance.......................................................................................................................... 8-13
Appendix A. HDL Attributes for Synplify
and Precision RTL Synthesis ........................................................ 8-15
VHDL Synplify/Precision RTL Synthesis.......................................................................................................... 8-15
Syntax ..................................................................................................................................................... 8-15
Examples ................................................................................................................................................ 8-15
Verilog for Synplify ........................................................................................................................................... 8-18
Syntax ..................................................................................................................................................... 8-18
Examples ................................................................................................................................................ 8-18
Verilog for Precision RTL Synthesis................................................................................................................. 8-20
Syntax ..................................................................................................................................................... 8-20
Example .................................................................................................................................................. 8-20
Appendix B. sysIO Attributes Using Preference Editor User Interface.............................................................8-22
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-23
IOBUF ..................................................................................................................................................... 8-23
LOCATE.................................................................................................................................................. 8-23
USE DIN CELL........................................................................................................................................ 8-24
USE DOUT CELL.................................................................................................................................... 8-24
PGROUP VREF ...................................................................................................................................... 8-24
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| RBB85DHBS | CONN EDGECARD 170PS R/A .050 DIP |
| AS1359-BTTT-45 | IC REG LDO 4.5V .3A TSOT23-5 |
| MIC2211-GSYML TR | IC REG LDO 1.8V/3.3V 10-MLF |
| AS1359-BTTT-27 | IC REG LDO 2.7V .3A TSOT23-5 |
| HSC40DRYS-S734 | CONN EDGECARD 80POS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LFXP20C-3F388C | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 19.7K LUTs 268 IO 1. 8/2.5/3.3V -3 Spd RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFXP20C-3F388I | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 19.7K LUTs 268 IO 1. 8/2.5/3.3V -3 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFXP20C-3F484C | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 19.7K LUTs 340 I/O 1.8/2.5/3.3V -3 Spd RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFXP20C-3F484I | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 19.7K LUTs 340 IO 1. 8/2.5/3.3V -3 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFXP20C-3FN256C | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 19.7K LUTS 188 I/O RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
