LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysIO Usage Guide
8-9
REXT = (VEXT - VINMAX)/ID = (5.25V - 3.75V)/27.4 = 54.8 ohm
If the VCCIO of the bank is increased, it will also increase the value of the external resistor required. Changing the
bank VCCIO will also change the value of the input threshold voltage.
Programmable Input Delay
Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the
input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at
zero hold time, the input delay will delay the data by at least as much as the primary clock injection delay. This
option can be turned ON or OFF for each I/O independently in the software using the FIXEDDELAY attribute. This
attribute is described in more detail in the Software sysIO Attributes section. Appendix A shows how this feature
can be enabled in the software using HDL attributes.
Software sysIO Attributes
sysIO attributes can be specified in the HDL, using the Preference Editor GUI or in the ASCII Preference file (.prf)
file directly. Appendices A, B and C list examples of how these can be assigned using each of the methods men-
tioned above. This section describes in detail each of these attributes.
IO_TYPE
This is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are embedded in
the attribute names itself. There is no separate attribute to set the VCCIO requirements. Table 8-6 lists the available I/O types.
