參數(shù)資料
型號(hào)： LFX200EB-05FN256C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 31/119頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 210KGATES 256FPBGA
標(biāo)準(zhǔn)包裝： 90
系列： ispXPGA®
邏輯元件/單元數(shù)： 2704
RAM 位總計(jì)： 113664
輸入/輸出數(shù)： 160
門數(shù)： 210000
電源電壓： 2.3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
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Lattice Semiconductor
ispXPGA Family Data Sheet
15
Figure 17. ispXPGA PLL_RST and PLL_FBK Generation
Clock Routing
The Global Clock Lines (GCLK) have two sources, their dedicated pins and the sysCLOCK circuit. Figure 18 illus-
trates the generation of the Global Clock Lines.
Figure 18. Global Clock Line Generation
sysIO Capability
All the ispXPGA devices have eight sysIO banks, where each bank is capable of supporting multiple I/O standards.
Each sysIO bank has its own I/O supply voltage (VCCO) and reference voltage (VREF) resources allowing each
bank complete independence from the others. Each I/O is individually configurable based on the bank’s VCCO and
VREF settings. In addition, each I/O has configurable drive strength, weak pull-up, weak pull-down, or a bus-keeper
latch. Table 4 lists the number of I/Os supported per bank in each of the ispXPGA devices. In addition, 5V tolerant
inputs are specified within an I/O bank that is connected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI
interfaces.
Table 5 lists the sysIO standards with the typical values for VCCO, VREF and VTT.
The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not
have the sysIO capabilities. The TOE and CFG0 pins operate off the VCC of the device, supporting only the LVC-
MOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (VCCJ),
which determines the LVCMOS standard corresponding to that supply voltage.
There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the un-
terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVC-
MOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface.
I/O/PLL_RST
I/O/PLL_FBK
From Routing
From Clock Net
To PLL
PLL0
GCLK0
CLK_OUT0
SEC_OUT0
PLL1
CLK_OUT1
SEC_OUT1
GCLK1
PLL2
CLK_OUT2
SEC_OUT2
GCLK2
PLL3
CLK_OUT3
SEC_OUT3
GCLK3
PLL7
GCLK7
CLK_OUT7
SEC_OUT7
PLL6
CLK_OUT6
SEC_OUT6
GCLK6
PLL5
CLK_OUT5
SEC_OUT5
GCLK5
PLL4
CLK_OUT4
SEC_OUT4
GCLK4
CLK0
CLK1
CLK2
CLK3
CLK7
CLK6
CLK5
CLK4
From Routing
DEVICES
DISCONTINUED
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFX200EB-05FN516C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 E-Ser210K Gt ispJTA G 2.5/3.3V -5 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX200EB-3F256C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX200EB-3F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX200EB-3F516C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
LFX200EB-3F516I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ispXPGA Family
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