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  • 參數(shù)資料
    型號(hào): LFECP20E-4FN672C
    廠商: Lattice Semiconductor Corporation
    文件頁數(shù): 70/163頁
    文件大?。?/td> 0K
    描述: IC FPGA 19.7KLUTS 672FPBGA
    標(biāo)準(zhǔn)包裝: 40
    系列: ECP
    邏輯元件/單元數(shù): 19700
    RAM 位總計(jì): 434176
    輸入/輸出數(shù): 400
    電源電壓: 1.14 V ~ 1.26 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 672-BBGA
    供應(yīng)商設(shè)備封裝: 672-FPBGA(27x27)
    September 2012
    Data Sheet DS1000
    2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
    or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
    www.latticesemi.com
    7-1
    Revision History
    Date
    Version
    Section
    Change Summary
    June 2004
    01.0
    Initial release.
    August 2004
    01.1
    Introduction
    Added new device LFECP/LFEC33 in Table 1-1.
    Architecture
    Added New device LFECP/LFEC33 in Tables 2-9, 2-10 and 2-11.
    DC & Switching
    Characteristics
    Added New device LFECP/LFEC33 on Supply current (Standby) tables.
    Added New device LFECP/LFEC33 on Initialization Supply current
    tables.
    Ordering Information
    Added 33K Logic Capacity Device in Part Number Description section.
    Added EC33, ECP33 device: Industrial and Commercial to Part Number
    table.
    Corrected I/O counts in the part number tables for 100/144 TQFP and
    208 PQFP packages to match Table 1-1 on page 1.
    November 2004
    01.3
    Introduction
    Changed DDR333 (166MHz) to DDR400 (200MHz)
    Added “RSDS” offering to the Features list: Flexible I/O Buffer
    Architecture
    Added information about Secondary Clock Sources
    Added information about DCS
    Added a section on “Recommended Power-up Sequence”
    Updated Figure 2-24 “DQS Routing”
    Added DSP Block performance numbers to Table 2-11
    Added another row for RSDS in Table 2-13 and Table 2-14
    DC & Switching
    Characteristics
    Updated new timing numbers
    Added numbers to derating table
    Added DC conditions to RSDS table
    Changed LVDS Max. VCCIO to 2.625
    Added a row for RSDS in “Operating Condition” table
    Updated standby and initialization current table
    Added figure 3-12: sysConfig SPI port sequence
    Added DDR Timing Table and DDR Timings Figure 3-6
    Pinout Information
    Added LFECP/EC6 to Pin Information
    Added LFECP/EC6 to Power Supply and NC Connections
    Added LFECP/EC6 144 TQFP Logic Signal Connections
    Added LFECP/EC6 208 PQFP Logic Signal Connections
    Added LFECP/EC6 256 fpBGA Logic Signal Connections
    Added LFECP/EC6 484 fpBGA Logic Signal Connections
    Ordering Information
    Added 33K Logic Capacity Device in Part Number Description section.
    Added Part Number table for Commercial EC33.
    Added Part Number table for Commercial ECP33.
    Added Part Number table for Industrial EC33.
    Added Part Number table for Industrial ECP33.
    LatticeECP/EC Family Data Sheet
    Revision History
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    參數(shù)描述
    LFECP20E-4FN672I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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