Table 2-12. PIO Signal List Figure 2-25. DQS Routing PIO The PIO contains four blocks:" />
參數(shù)資料
型號： LFECP15E-4FN256C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 82/163頁
文件大?。?/td> 0K
描述： IC FPGA 15.3KLUTS 256FPBGA
標準包裝： 90
系列： ECP
邏輯元件/單元數(shù)： 15400
RAM 位總計： 358400
輸入/輸出數(shù)： 195
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應商設(shè)備封裝： 256-FPBGA（17x17）
2-22
Architecture
LatticeECP/EC Family Data Sheet
Table 2-12. PIO Signal List
Figure 2-25. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Name
Type
Description
CE0, CE1
Control from the core
Clock enables for input and output block FFs.
CLK0, CLK1
Control from the core
System clocks for input and output blocks.
LSR
Control from the core
Local Set/Reset.
GSRN
Control from routing
Global Set/Reset (active low).
INCK
Input to the core
Input to Primary Clock Network or PLL reference inputs.
DQS
Input to PIO
DQS signal from logic (routing) to PIO.
INDD
Input to the core
Unregistered data input to core.
INFF
Input to the core
Registered input on positive edge of the clock (CLK0).
IPOS0, IPOS1
Input to the core
DDRX registered inputs to the core.
ONEG0
Control from the core
Output signals from the core for SDR and DDR operation.
OPOS0,
Control from the core
Output signals from the core for DDR operation
OPOS1 ONEG1
Tristate control from the core
Signals to Tristate Register block for DDR operation.
TD
Tristate control from the core
Tristate signal from the core used in SDR operation.
DDRCLKPOL
Control from clock polarity bus
Controls the polarity of the clock (CLK0) that feed the DDR input block.
PIO A
PIO B
PADA "T"
PADB "C"
PIO B
PIO A
PIO B
PIO A
Assigned
DQS Pin
DQS
sysIO
Buffer
LVDS Pair
PADA "T"
PADB "C"
LVDS Pair
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
Delay
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參數(shù)描述
LFECP15E-4FN256I 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 195 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFECP15E-4FN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs Pb-Free RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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LFECP15E-4FN672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
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