Figure 2-27. Input Register DDR Waveforms Figure 2-28. INDDRXB Primitive Output Regist" />
參數(shù)資料
型號: LFECP15E-3FN484I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 84/163頁
文件大?。?/td> 0K
描述: IC FPGA 15.3KLUTS 484FPBGA
標準包裝: 60
系列: ECP
邏輯元件/單元數(shù): 15400
RAM 位總計: 358400
輸入/輸出數(shù): 352
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應商設備封裝: 484-FPBGA(23x23)
2-24
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-27. Input Register DDR Waveforms
Figure 2-28. INDDRXB Primitive
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-29 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
AB
C
D
E
F
BD
DI
(In DDR Mode)
D0
D2
DQS
A
C
DQS
Delayed
IDDRXB
LSR
QA
D
ECLK
QB
DDRCLKPOL
SCLK
CE
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