Figure 2-31. Tristate Register Block Control Logic Block The control logic block allows the s" />
參數(shù)資料
型號(hào)： LFEC3E-5TN144C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 86/163頁
文件大?。?/td> 0K
描述： IC FPGA 3.1KLUTS 97I/O 144-TQFP
標(biāo)準(zhǔn)包裝： 60
系列： EC
邏輯元件/單元數(shù)： 3100
RAM 位總計(jì)： 56320
輸入/輸出數(shù)： 97
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
2-26
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-31. Tristate Register Block
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from
the programmable DQS pin. The clock can optionally be inverted.
The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate
signal is passed through this block.
DDR Memory Support
Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input
(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeEC
devices provide this capability. In addition to these registers, the LatticeEC devices contain two elements to simplify
the design of input structures for read operations: the DQS delay block and polarity control logic.
DLL Calibrated DQS Delay Block
Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However in DDR memories the clock
(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS routing
resource. The DQS signal also feeds polarity control logic, which controls the polarity of the clock to the sync regis-
ters in the input register blocks. Figures 2-32 and 2-33 show how the DQS transition signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-33. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
D
LE*
Q
D
Q
D-Type
ONEG1
CLK1
Programmed
Control
TO
Latch
*Latch is transparent when input is low.
OPOS1
OUTDDN
/LATCH
0
1
0
1
From
Routing
To sysIO
Buffer
TD
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