Figure 2-20. MAC sysDSP Element MULTADD sysDSP Element In this case, the operands A0 and B0 a" />
參數(shù)資料
型號: LFEC3E-4TN144C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 77/163頁
文件大?。?/td> 0K
描述: IC FPGA 3.1KLUTS 97I/O 144-TQFP
標準包裝: 60
系列: EC
邏輯元件/單元數(shù): 3100
RAM 位總計: 56320
輸入/輸出數(shù): 97
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應商設(shè)備封裝: 144-TQFP(20x20)
2-17
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-20. MAC sysDSP Element
MULTADD sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21
shows the MULTADD sysDSP element.
Figure 2-21. MULTADD
Multiplier
x
n
m
m+n
(default)
m+n+16 bits
(default)
m+n+16 bits
(default)
Input Data
Register B
Input Data
Register A
m
n
m
n
m
Overflo
w
Register
Output
Register
Accumulator
Multiplier
Multiplicand
SignedAB
Shift Register A In
Shift Register B In
Shift Register A Out
Shift Register B Out
Output
Addn
Accumsload
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
To
Accumulator
To
Accumulator
To
Accumulator
Overflow
signal
Multiplier
Add/Sub
Pipe
Reg
Pipe
Reg
n
m
n
m
n
m
n
m
m+n
(default)
m+n+1
(default)
m+n+1
(default)
m+n
(default)
x
n
m
n
m
n
n
m
Multiplier B0
Multiplicand A0
Multiplier B1
Multiplicand A1
Signed
Shift Register A In
Shift Register B In
Shift Register A Out
Shift Register B Out
Output
Addn
Pipeline
Register
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
Pipeline
Register
Input Data
Register A
Input Data
Register A
Input Data
Register B
Input Data
Register B
Output
Register
To Add/Sub
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LFEC3E-4TN144I 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs 97 IO 1.2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1K LUTs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5F256CES 功能描述:FPGA - 現(xiàn)場可編程門陣列 3.1 LUT 160 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFEC3E-5F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC3E-5F484C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet