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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | LFEC33E-4FN672C |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋佹暩(sh霉)锛� | 90/163闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 32.8KLUTS 672FPBGA |
| 妯欐簴鍖呰锛� | 40 |
| 绯诲垪锛� | EC |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 32800 |
| RAM 浣嶇附瑷堬細 | 434176 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 496 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.26 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 85°C |
| 灏佽/澶栨锛� | 672-BBGA |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 672-FPBGA锛�27x27锛� |
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2-29
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-34. LatticeECP/EC Banks
LatticeECP/EC devices contain two types of sysI/O buffer pairs.
1.
Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers
and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also
be configured as a differential input.
The two pads in the pair are described as 鈥渢rue鈥� and 鈥渃omp鈥�, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot
socketing with IDK less than 1mA. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid
operating levels and the device has been configured.
2.
Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as 鈥渢rue鈥� and 鈥渃omp鈥�, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers. See the IDK specification for I/O leakage cur-
rent during power-up.
V
REF1(2)
GND
Bank
2
V
CCIO2
V
REF2(2)
V
REF1(3)
GND
Bank
3
V
CCIO3
V
REF2(3)
V
REF1(7)
GND
TOP
LEFT
RIGHT
BOTTOM
Bank
7
V
CCIO7
V
REF2(7)
V
REF1(6)
GND
Bank
6
V
CCIO6
V
REF2(6)
V
REF1(5)
GND
Bank 5
V
CCIO5
V
REF2(5)
V
REF1(4)
GND
Bank 4
V
CCIO4
V
REF2(4)
V
REF1(0)
GND
Bank 0
V
CCIO0
V
REF2(0)
V
REF1(1)
GND
Bank 1
V
CCIO1
V
REF2(1)
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| EEC36DTEH | CONN EDGECARD 72POS .100 EYELET |
| GCB64DHBR | CONN EDGECARD 128PS R/A .050 SLD |
| 24LC02BT-I/OT | IC EEPROM 2KBIT 400KHZ SOT23-5 |
| EMC50DRSN-S273 | CONN EDGECARD 100PS DIP .100 SLD |
| EMC50DRSD-S273 | CONN EDGECARD 100PS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LFEC33E-4FN672I | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 32.8K LUTs 1.2V -4 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFEC33E-4Q208C | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFEC33E-4Q208I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFEC33E-4QN208C | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFEC33E-4QN208I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
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