tSOE CSSPIN Active S" />
參數(shù)資料
型號: LFEC20E-5FN672C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 122/163頁
文件大小: 0K
描述: IC FPGA 19.7KLUTS 672FPBGA
標(biāo)準(zhǔn)包裝: 40
系列: EC
邏輯元件/單元數(shù): 19700
RAM 位總計(jì): 434176
輸入/輸出數(shù): 400
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-FPBGA(27x27)
3-25
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Master Clock
tSOE
CSSPIN Active Setup Time
300
ns
tCSPID
CSSPIN Low to First Clock Edge Setup Time
300+3cyc
600+6cyc
ns
fMAXSPI
Max Frequency for SPI
25
MHz
tSUSPI
SOSPI Data Setup Time Before CCLK
7
ns
tHSPI
SOSPI Data Hold Time After CCLK
1
ns
Timing v.G 0.30
Clock Mode
Min.
Typ.
Max.
Units
2.5MHz
1.75
2.5
3.25
MHz
5 MHz
3.78
5.4
7.02
MHz
10 MHz
7
10
13
MHz
15 MHz
10.5
15
19.5
MHz
20 MHz
142026
MHz
25 MHz
18.2
26
33.8
MHz
30 MHz
213039
MHz
35 MHz
23.8
34
44.2
MHz
40 MHz
28.7
41
53.3
MHz
45 MHz
31.5
45
58.5
MHz
50 MHz
35.7
51
66.3
MHz
55 MHz
38.5
55
71.5
MHz
60 MHz
426078
MHz
Duty Cycle
40
60
%
Timing v.G 0.30
LatticeECP/EC sysCONFIG Port Timing Specifications (Continued)
Over Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Units
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