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參數(shù)資料
| 型號： | LFEC20 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EP300 PowerPC Bus Arbiter |
| 中文描述： | EP300 PowerPC的總線仲裁器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 135K |
| 代理商： | LFEC20 |
Copyright by Eureka Technology Inc.
4962 El Camino Real,
Los Altos, CA 94022, USA
Tel: 1 650 960 3800
Fax: 1 650 960 3805
http://www.eurekatech.com
Page 1
Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740,
750 and 8260.
Supports up to eight PowerPC bus masters with unlimited slave device support.
Supports two outstanding bus accesses.
Supports address only transfer and address bus retry.
Independent address bus and data bus tenure with separate bus grant and data
bus grant.
Option for fixed priority assignment or rotating priority scheme.
Designed for ASIC or programmable logic device implementations in various
system environments.
Fully static design with edge triggered flip-flops.
Optimized for ispXPGA product family.
The EP300 PowerPC bus arbiter provides all the necessary functions to arbitrate
multiple bus masters directly connected to the PowerPC host bus. The arbiter sup-
ports separate address and data bus tenure to realize the high performance allowed
by the PowerPC bus architecture. Separate address bus grant and data bus grant
signals are provided for each master device on the bus. The arbiter uses sophisti-
cated built-in state machines to coordinate the address bus tenure and the data bus
tenure. At any given cycle, up to two simultaneous bus accesses are allowed.
FEATURES
DESCRIPTIONS
EP300 PowerPC Bus Arbiter
Product Summary
Previous
master
data bus
grant
Address bus
Priority
Data bus grant
One to each device
Bus request
One from each device
TS# ABB# DBB# TT
PowerPC Bus
Bus grant
One to each device
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFO-14-I | CW output power > 0.8 mW |
| LFO-17-IP | CW output power > 2.0 mW |
| LFO-18-I | CW output power > 0.8 mW |
| LFO-65-D | CW output power > 1.0mW |
| LFTC-1350 | Low Pass Filter(DC to 1350 MHz) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC20E-3F256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-3F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC20E-3F484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-3F484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 360 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFEC20E-3F672C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7 LUT 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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