- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19287 > LFEC1E-4TN144I (Lattice Semiconductor Corporation)IC FPGA 1.5KLUTS 144TQFP PDF資料下載
參數(shù)資料
| 型號： | LFEC1E-4TN144I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 89/163頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.5KLUTS 144TQFP |
| 標準包裝： | 60 |
| 系列： | EC |
| 邏輯元件/單元數(shù)： | 1500 |
| RAM 位總計： | 18432 |
| 輸入/輸出數(shù)： | 97 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當(dāng)前第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁
2-28
Architecture
LatticeECP/EC Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup
and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysI/O Buffer Banks
LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each
sysI/O bank has its own I/O supply voltage (VCCIO), and two voltage references VREF1 and VREF2 resources allow-
ing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associ-
ated supplies.
In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-
X) are powered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold
input independent of VCCIO. In addition to the bank VCCIO supplies, the LatticeECP/EC devices have a VCC core logic
power supply, and a VCCAUX supply that power all differential and referenced buffers.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a
reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference volt-
ages.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFEC3E-3TN100C | IC FPGA 3.1KLUTS 67I/O 100-TQFP |
| LFEC1E-5TN144C | IC FPGA 1.5KLUTS 97I/O 144-TQFP |
| HCC65DRTF | CONN EDGECARD 130PS DIP .100 SLD |
| FMC15DRYS | CONN EDGECARD 30POS DIP .100 SLD |
| IR2166 | IC PFC/BALLAST CONTROL 16-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFEC1E-5F256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC1E-5F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC1E-5F484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC1E-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
| LFEC1E-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。