參數(shù)資料
型號(hào): LFEC1E-3TN144I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 104/163頁
文件大小: 0K
描述: IC FPGA 1.5KLUTS 97I/O 144-TQFP
標(biāo)準(zhǔn)包裝: 60
系列: EC
邏輯元件/單元數(shù): 1500
RAM 位總計(jì): 18432
輸入/輸出數(shù): 97
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
3-9
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
BLVDS
The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one
possible solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Table 3-2. BLVDS DC Conditions1
Over Recommended Operating Conditions
Typical
Parameter
Description
Zo = 45
Zo = 90
Units
ZOUT
Output impedance
100
ohm
RTLEFT
Left end termination
45
90
ohm
RTRIGHT
Right end termination
45
90
ohm
VOH
Output high voltage
1.375
1.48
V
VOL
Output low voltage
1.125
1.02
V
VOD
Output differential voltage
0.25
0.46
V
VCM
Output common mode voltage
1.25
V
IDC
DC output current
11.2
10.2
mA
1. For input buffer, see LVDS table.
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
100
2.5V
+
-
100
2.5V
+ -
100
2.5V
+
-
100
2.5V
+
-
. . .
45-90 ohms, +/- 1%
+ -
+
-
. . .
-
%
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