參數(shù)資料
型號(hào): LFEC1E-3QN208I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 13/163頁
文件大?。?/td> 0K
描述: IC FPGA 1.5KLUTS 208PQFP
標(biāo)準(zhǔn)包裝: 48
系列: EC
邏輯元件/單元數(shù): 1500
RAM 位總計(jì): 18432
輸入/輸出數(shù): 112
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
2-8
Architecture
LatticeECP/EC Family Data Sheet
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
From
Routing
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