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參數(shù)資料
| 型號： | LF6197CCJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | 160 ns Monolithic Sample-and-Hold Amplifier |
| 中文描述： | SAMPLE AND HOLD AMPLIFIER, 0.145 us ACQUISITION TIME, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 214K |
| 代理商： | LF6197CCJ |
Functional Description
The LF6197 uses a proprietary ‘‘current-multiplexed sam-
ple-and-hold’’ technique as depicted in the simplified block
diagram (Figure 2). The amplifier consists of two transcon-
ductance input stages g
m1
and g
m2
and a common gain and
output buffer stage A3. In the sample mode, internal current
switching is employed to connect the input stage g
m1
to the
common output stage A3 while input stage g
m2
is discon-
nected. Additionally, switches S2 and S3 are closed, there-
by shorting the internal dummy capacitor and connecting
one end of the hold capacitor to a low impedance ground.
Although the simplified schematic shows the switches S1
and S2 connected to ground, the switches are in fact con-
nected to a reference potential which appears as a common
mode voltage at the two inputs of g
m2
.
For unity gain, the inverting input of g
m1
is externally con-
nected to the output through a resistor, thus closing the loop
around the amplifier. Conventional op-amp feedback topolo-
gies may be employed to configure the amplifier for invert-
ing and non-inverting gains. In the sample mode, a current
booster in the output stage rapidly charges the hold capaci-
tor. A wide-bandwidth amplifier, high-current output stage
and fast current-switched hold-to-sample mode selection al-
lows for a slew rate of 145 V/
m
s and acquisition time of
under 200 ns.
When there is a change to the Hold mode, switches S2 and
S3 are quickly opened and switch S1 is effectively connect-
ed to the output of g
m2
while input stage g
m1
is disconnect-
ed. The composite amplifier is now comprised of g
m2
and
A3 and the loop around the amplifier is closed by the hold
capacitor. Note that the opening of switch S3 causes
charge injection into the hold capacitor. However, an equal
amount of charge is injected into the dummy capacitor due
to the opening of a matched switch S2. The net effect is a
differential cancellation of charge and thus the pedestal er-
ror (hold step) is greatly reduced. Meanwhile, excellent
feedthrough attenuation is achieved because the input sig-
nal is isolated from the output by the inactive input stage
g
m1
.
TL/H/11381–5
FIGURE 2. Simplified Block Diagram of LF6197 Sample-and-Hold Amplifier, Connected for Unity Gain and TTL Logic
8
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