參數(shù)資料
型號(hào)： T431616C-7SG
廠商： TM Technology, Inc.
英文描述： 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
中文描述： 100萬(wàn)× 16內(nèi)存為512k × 16Bit的X 2Banks同步DRAM
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 720K
代理商： T431616C-7SG
TE
CH
tm
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Auto Refresh
T431616C
TM Technology Inc. reserves the right
P.13
to change products or specifications without notice.
Publication Date: AUG. 2004
Revision: A
CKEn-1 CKEn
CS
RAS
CAS
WE DQM BA A
10
/AP A
9
~A
0
Note
H
X
L
L
L
L
H
H
L
X
X
1,2
Entry
L
L
L
H
X
X
3
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Self
Refresh
Exit
L
H
X
X
3
Bank Active & Row Address
H
X
X
V
Row Address
Auto Precharge Disable
Auto Precharge Enable
L
H
L
H
Read Column
Address
Write & Column
Address
Burst Stop
H
X
L
H
L
H
X
V
Column
Address
(A0~A7)
Column
Address
(A0~A7)
4,5
Auto Precharge Disable
Auto Precharge Enable
H
X
L
H
L
L
X
V
4,5
H
X
L
H
H
L
X
X
6
Bank Selection
Both Banks
V
X
L
H
Precharge
H
X
L
L
H
L
X
4
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock Suspend or
Active Power Down
Exit
Entry
L
H
X
X
H
L
X
Precharge Power Down
Mode
Exit
L
H
X
X
DQM
H
V
X
7
H
H
H
L
X
H
X
H
X
H
No Operation Command
X
X
X
(V=Valid , X=Don’t Care , H=Logic High , L=logic Low)
Notes :
1. OP Code : Operation Code. A
0
~A
10
/AP , BA : Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row
precharge command is meant by ‘Auto’. Auto / self refresh can be issued only at both banks precharge state.
4. BA : Bank select address.
If ’Low’ : at read , wriye , row active and precharge , bank A is selected.
If ‘High’ : at read , wriye , row active and precharge , bank B is selected.
If A
10
/AP is ‘High’ : at row precharge , BA ignored and both banks are selected.
5. During burst read or write with auto precharge , new read/write command cannotbeissued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at
t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
相關(guān)PDF資料
PDF描述
T431616D 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5C 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5CG 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5S 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5SG 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T431616D 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5C 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5CG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5S 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
T431616D-5SG 制造商:TMT 制造商全稱:TMT 功能描述:1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
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