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參數(shù)資料
| 型號： | LC99012A-S |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Black-and-White CCD Timing Generator |
| 中文描述： | 黑與白CCD時序發(fā)生器 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大小： | 59K |
| 代理商： | LC99012A-S |
No. 5281-6/6
LC99012A-S
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
I
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
I
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
I
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Pin No.
Symbol
I/O
Function
39
VS1
O
CCD imaging block transfer clock (S1)
40
VS2
O
CCD imaging block transfer clock (S2)
41
VS3
O
CCD imaging block transfer clock (S3)
42
GND
43
DHTR
CCD output block reset pulse
44
DHT1
O
CCD horizontal transfer clock (H1)
45
DHT2
O
CCD horizontal transfer clock (H2)
46
V
DD
DS2
47
O
CCD output floating level sampling pulse
48
DS1
O
CCD output video signal sampling pulse
49
GND
50
CLP1
O
OPB clamp pulse
51
CLP2
O
OPB clamp pulse
52
PBLK
O
Pre-blanking pulse
53
CBLK
O
Composite blanking pulse
54
C.SYNC
O
Composite sync pulse
55
TV
I
Low: EIA (LC9947G/49G)
High: CCIR (LC9948G)
56
V
DD
AGCC2
57
O
AGC detection signal weighting processing pulse
Electronic iris state output
High: The iris is in the fully stopped down state.
Low: The iris is in the fully open state.
High-impedance: The iris is in an appropriate state.
58
IRSTA
O
59
VIDI
I
Analog switch input for iris detection signal window processing
60
VIDO
O
Analog switch output for iris detection signal window processing
61
IRRES
O
Reset (discharge) pulse that is input by the iris signal detection (integration) circuit
62
IRIS
I
Iris integration signal input
63
DCH
I
High-level reference voltage for the iris level detection comparator
64
DCL
I
Low-level reference voltage for the iris level detection comparator
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