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參數(shù)資料
| 型號： | LC89972M |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 104K |
| 代理商： | LC89972M |
Ordering number : EN 51134465
72595TH (OT) No. 5113-1/8
Overview
The LC89972M is a CCD delay line for PAL television
systems. It incorporates a comb filter for chrominance signal
and a 1H delay line for luminance signal.
Structure
NMOS + CCD
Functions
Two CCD shift registers (for chrominance and
luminance signals)
CCD drive circuits
CCD stage count switching circuit
CCD signal adder
Auto-bias circuit
Sync tip clamping circuit (luminance signal)
Center-bias circuit (chrominance signal)
Sample-and-hold circuit
PLL 3
× frequency multiplier
3 fsc clock output circuit
RD voltage generator
Features
5 V single-voltage power supply
Built-in PLL 3
× frequency multiplier circuit allows
3 fsc operation from an fsc (4.43 MHz) input.
Control pin switchable to handle PAL/GBI and
4.43 MHz NTSC systems.
Built-in chrominance signal crosstalk exclusion comb
filter features high-precision comb characteristics in an
adjustment-free circuit.
Built-in peripheral circuits allow applications to be
constructed with a minimum number of external
components.
Positive-phase signal input/positive-phase signal output
(luminance signal)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Package Dimensions
unit: mm
3045B-MFP24
SANYO: MFP24
[LC89972M]
LC89972M
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
PAL CCD Delay Line
MOS IC
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VDD max
–0.3 to +6.0
V
Allowable power dissipation
Pd max
600
mW
Operating temperature
Topr
–10 to +70
°C
Storage temperature
Tstg
–55 to +150
°C
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