參數(shù)資料
型號: LC89950
廠商: Sanyo Electric Co.,Ltd.
英文描述: 1H Delay Line for PAL Systems
中文描述: 上半年延遲線為PAL系統(tǒng)
文件頁數(shù): 2/5頁
文件大?。?/td> 98K
代理商: LC89950
No. 5440-2/5
LC89950
Electrical Characteristics
at Ta = 25°C, V
DD
= 5.0 V, Fscp = 15.625 kHz
Parameter
Symbol
Switch States
min
typ
max
Unit
Test
SW1
SW2
SW3
SW4
conditions
Current drain
I
DD
a/b
a
a/b
a/b
1
5
10
15
mA
Output pin voltage (pin 1)
V
OUT
(R-Y)
V
OUT
(B-Y)
V
IN
(R-Y)
V
IN
(B-Y)
G
V
(R-Y)
G
V
(B-Y)
G
V
G
f
(R-Y)
G
f
(B-Y)
+L6 (R-Y)
b
a
a/b
a/b
2
0.7
1.7
2.7
V
Output pin voltage (pin 3)
a
a
a/b
a/b
2
0.7
1.7
2.7
V
Input pin voltage (pin 7)
b
a
a/b
a/b
2
1.4
2.4
3.4
V
Input pin voltage (pin 5)
a
a
a/b
a/b
2
1.4
2.4
3.4
V
Voltage gain
a
a
a
a
3
–2
0
+2
dB
b
a
a
a
3
–2
0
+2
dB
Differential voltage gain
a
b
a
a
a
a
3
0.1
0.3
dB
Frequency characteristics
a
a
a
4
–3
–1
dB
b
a
a
a
4
–3
–1
dB
Positive phase input linearity +L6
a
a
a
b
5
57
60
63
%
+L6 (B-Y)
b
a
a
b
5
57
60
63
%
Inverted input linearity –L6
–L6 (R-Y)
a
a
b
b
5
57
60
63
%
–L6 (B-Y)
b
a
b
b
5
57
60
63
%
Clock leakage (4 MHz)
Lclk (R-Y)
a
a
a
a
6
7
12
mVrms
Lclk (B-Y)
b
a
a
a
6
7
12
mVrms
Noise level
No (R-Y)
a
a
a
b
7
1
2
mVrms
No (B-Y)
b
a
a
b
7
1
2
mVrms
μs
Output impedance
Z
OUT
(R-Y)
Z
OUT
(B-Y)
Td (R-Y)
a
a
b
a
b
a
a
a
8
200
300
400
b
a
a
8
200
300
400
Delay time
a
a
a
9
63.80
Td (B-Y)
b
a
a
a
9
63.80
μs
Sandcastle Pulse (Input Clock) Conditions
Notes: 1. Indicates the synchronization range for the PLL circuit. The delay time changes with the input frequency.
2. Vhigh is the minimum value between c and d.
3. Vmid is the maximum value between a and b and between e and f.
Parameter
Symbol
Conditions
min
typ
max
Unit
Input frequency
*
1
Fscp
14.625
15.625
16.625
kHz
Input pulse width
TW bgp
3.0
4.0
5.0
μs
High level
*
2
Vhigh
5.9
6.5
7.5
V
Mid level
*
3
Vmid
2.5
3.5
4.4
V
Low level
Vlow
–0.3
0
2.5
V
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