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參數(shù)資料
| 型號(hào)： | LC898023KL |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | LC898023KL |
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No. 6614-12/13
LC898023KW, 898023KL
5. Spindle Speed Detection Pins
FG (input)
Input for the speed monitor signal from the spindle driver.
6. Audio Interface Pins
LOUT, ROUT (output)
Left and right channel audio signal outputs.
7. RF Amplifier Interface Pins
LDON (output)
RF amplifier interface.
8. Write Strategy Pins
WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, 1, WDAT, NWDAT (I/O)
Write strategy signal connections.
9. ATIP Decoder Related Pins
ATIPSYNC (output)
ATIP synchronization detection signal. (For monitoring)
BIDATA, BICLK (I/O)
Input mode: Input of the biphase data and biphase clock when an external ATIP demodulator is used.
Output mode: Output of the biphase data and biphase clock when the internal ATIP demodulator is used. (For
monitoring)
WOBBLE (input)
Wobble signal is input when the internal ATIP demodulator is used.
ACRCNG (output)
Outputs the result of the ATIP decoder CRC check. (For monitoring)
<Other Pins>
RESET (input)
The LC898023K reset input. A low level input resets the LC898023K.
This pin must be held low for at least 1 s when power is first applied.
TEST4 to TEST0 (input)
Test inputs. These pins must be connected to ground.
XTALCK0 (input), XTAL0 (output)
Drive these pins at 33.8688 MHz. This signal is used, without modification, as main clock for the CD-ROM encoder
and decoder blocks, including the DRAM interface.
XTALCK1 (input), XTAL1 (output)
Main clock for the SCSI block. The LC898023K is designed so that it can operate even when the ECC and SCSI
blocks are not synchronized. Providing a 20 MHz input to the XTALCK0 and XTALCK1 pins assures that correct,
synchronized transfer at 10 Mbyte/s (20 Mbyte/s for Ultra SCSI) can be achieved. The maximum frequency that can
be used is 20 MHz.
Since both edges of the clock signal are used by Ultra SCSI, the duty ratio must be correct. Add feedback resistors on
the XTALCK1 and XTAL1 pins and take other measures as required.
R, VCNT, PDO, R1, VCNT1, PD1, MDC1 (I/O)
Clock reproduction PLL circuit pins.
SUBSYNC (output)
Subcode SYNC output signal from the CIRC encoder during recording. (For monitoring)
EFMG (output)
Outputs a high level during recording.
SHOCK (output)
Outputs a high level when a mechanical shock is detected.
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| LC898023KW | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
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| LC898093KW | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC898023KW | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:40ⅴ Playback/16ⅴ Write CD-R/RW Encoder/Decoder IC with Built-in SCSI Interface |
| LC898093 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:40ⅴ Playback/12ⅴ Write CD-R/RW Encoder/Decoder IC with Built-in ATAPI Interface |
| LC898093KL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC898093KW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC898094 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:LC898094 |
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