參數(shù)資料
型號: LC890561W
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, SQFP-48
文件頁數(shù): 24/47頁
文件大?。?/td> 357K
代理商: LC890561W
LC890561W
No8226-30/47
13.3 Time Lag of the Command Setup (DTMA[4:0], DTMB[3:0], DTMC[2:0], DTMX[4:0], DTMY[3:0])
DTMA [4:0], DTMB [3:0], DTMC [2:0], DTMX [4:0] and DTMY [3:0] commands are performed synchronizing with
the rising edge (the falling edge is used for the I2S data format setup) of LRCK clock. Therefore, the time lag of 1
LRCK cycle at the maximum arises after setting up the command until it is executed.
Moreover, the minimum interval of a command setup becomes 1 LRCK period.
Furthermore, data processing by command setup is performed after 1 LRCK period progress.
Setup, change and cancel of the delay time are processed per command.
Setup, change and cancel of the command in the same address are performed for the data of the target input sampling
frequency.
Cancel of the command is the case where the delay time is set as 0.
Figure 13.9 Timing Chart from a Command Setup to Execution
CE
CL
DI
B0
LRCK
B1
A2
A3
DI0
DI1
DI2
DI12 DI13 DI14 DI15
Time lag of command setting
Set-up of
Delay = 90ms
Delay = 40ms
Change point
Commands
interface
Microcontroller
State of
Commands
DATAO
Before (90ms)
After (40ms)
ex.) Delay = 90ms
ex.) Delay = 40ms
Time lag of data output
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