參數(shù)資料
型號(hào): LC89052TA-E
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO24
封裝: 0.225 INCH, TSSOP-24
文件頁(yè)數(shù): 19/42頁(yè)
文件大小: 224K
代理商: LC89052TA-E
LC89052TA-E
No.7457-26/42
8.7.3 Output of clock switch transition signal
This section describes the operation when
__________
UGPI is selected as an output pin during the clock switching transitional
period.
A clock switching transitional period signal is a signal that reports a clock switching condition to external circuits due
to a change in the PLL locked/unlocked state. This signal allows the application to grasp the PLL lock state
transitions and the timing of change in the clock signals. This setup is selected with GPISEL.
After setting GPISEL, high level is output from
__________
UGPI. Low pulse is output when the output clock changes due to the
change in the PLL circuit locked/unlocked state.
In the lock in process, the
__________
UGPI low pulse rises with the word clock generated by the XIN clock after input data is
detected and PLL is locked. After a certain period, it rises with the same timing as ERROR.
In the unlock process, the
__________
UGPI low pulse falls at the same timing as ERROR, which is the PLL lock detecting signal
and it rises after the word clocks generated from the XIN clock are counted for a certain period.
Figure 8.14 Clock Switching Timing
VCO clock
XTAL clock
CKOUT
(a) : During the lock-in process
UGPI
ERROR
PLL lock state
Unlocked
Locked
Unlocked
(b) : During the unlock process
RXIN
Digital data
After PLL lock
With the same timing
as ERROR
64/fs (s)
15 ms to 50 ms
VCO clock
XTAL clock
CKOUT
UGPI
ERROR
PLL lock state
RXIN
With the same timing as ERROR
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