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參數(shù)資料
| 型號(hào)： | LC89051V |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO24 |
| 封裝： | SSOP-24 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 274K |
| 代理商： | LC89051V |
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3. The following output settings can be controlled:
Channel status (C bit) output
Subcode Q data output
Start ID and shortening ID detection for DAT with subcodes
C bit output
This IC only handles the first 32 bits.
The flag is fixed at the high level (only when CKSEL is high), and the data format is LSB first.
Error and update checking is not applied to the data.
The internal shift register is reset if a PLL lock error occurs.
Since the channel status information consists of 192 frames, a fixed period must be provided between data readout
operations.
1
fs ×
192 (ms) < (the interval between data readout operations)
Subcode Q output
Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this
signal falls. However, this signal will not be output (fall) unless 96-bit subcode Q data (including the CRC check
bits) is input.
The flag outputs a high when the CRC check passes, and low if the CRC check fails. Besides, the shift clock SCLK
is required to be input regardless of the CRC flag status after latch pulse input.
The bit order is LSB first within each byte of the 80 bits of subcode Q data.
ID detection
The start ID and shortening ID are only detected when the DAT category code (1100000L) is received.
These IDs are detected as follows:
— A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync
signal (L0).
— After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for
subcode Q data to SWDT/DI.
Figure 4 User Data for DAT with Subcodes
The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and
the data output.
Output pins
The output scheme used for SRDT/DO differs depending on the microcontroller interface format selected by
No. 5543-13/15
LC89051V
(L0): SYNC
H
(R0): Start ID
H
L
(L1): Shortening ID
L
H
Flags + 80 data bits
all H
all L
Detected ID
Start ID
Shortening ID
CKSEL
Format
SRDT/DO
L
Figure 2
High open-drain output
H
Figure 3
Three-state output
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相關(guān)代理商/技術(shù)參數(shù) |
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| LC89052T | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC89052TA-E | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89052TA-TLM-E | 功能描述:音頻發(fā)送器、接收器、收發(fā)器 RoHS:否 制造商:Cirrus Logic 工作電源電壓:3.3 V, 5 V 電源電流:11.8 mA 通道數(shù)量:1 最大工作溫度:+ 70 C 接口類型:I2C, SPI 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-28 封裝: |
| LC89052THS-E | 制造商:ON Semiconductor 功能描述:AUDIO I/F RECEIVER |
| LC890561W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CMOS IC Digital Audio Interface Receiver with Built-in Data Buffer Memory |
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