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參數(shù)資料
| 型號： | LC86P5632 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8-Bit Single Chip Microcontroller with One-Time Programmable PROM |
| 中文描述： | 8位微控制器的單芯片一次性可編程胎膜早破 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大小： | 702K |
| 代理商： | LC86P5632 |
LC86P5632
No.6688-9/23
LC86P5632 Pin description
Pin name
I/O
VSS
-
VDD
-
VDDVPP
-
PORT0
P00 to P07
Function description
Option
PROM mode
Power pin (-)
Power pin (+)
Power pin (+)
I/O 8-bit input/output port
Input for port 0 interrupt
Input/output in nibble units
Input for HOLD release
-
-
-
Pull-up resistor :
Provided/Not provided
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
-
-
Power for programming
-
PORT1
P10 to P17
I/O 8-bit input/output port
Input/output can be specified in a bit unit
Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
I/O 8-bit input/output port
Input/output can be specified in a bit unit
Data line
D0 to D7
PORT2
P20 to P27
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Output form :
CMOS/N-channel open
drain
Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
P74
has no pull-up
resistor.
PORT3
P30 to P37
I/O 8-bit input/output port
Input/output can be specified in a bit unit
15V withstand at N-channel open drain output
I/O 8-bit input/output port
Input/output can be specified in a bit unit
15V withstand at N-channel open drain output
I/O 2-bit input/output port
Input/output can be specified in a bit unit
15V withstand at N-channel open drain output
5-bit input port
Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event
input
P74 : 32.768kHz crystal oscillation terminal XT1
Interrupt received forms,
the vector addresses
rising
falling
Address input
A7 to A0
PORT4
P40 to P47
Address input
A14 to A8 (*5)
P47 : TA (*4)
PORT5
P50 to P51
rising
&
falling
high
level
low
level
vector
INT0
INT1
INT2
INT3
enable enable disable enable enable
enable enable disable enable enable
enable enable enable disable disable
enable enable enable disable disable
03H
0BH
13H
1BH
PORT7
P70
P71 to
P74
I/O
I
Input of PROM
control signals
DASEC (*1)
OE
(*2)
CE
(*3)
Continue.
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