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參數(shù)資料
| 型號： | LC83025E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 282K |
| 代理商： | LC83025E |
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Allowable Operating Ranges
at Ta = –30 to +70°C, all VDD = 4.75 to 5.25 V, all VSS = 0 V unless otherwise specified
No. 4977-7/15
LC83025E
Parameter
Symbol
Conditions
Ratings
Unit
Note
Maximum supply voltage
VDD max
–0.3 to +7.0
V
VO1
OSC2 output
Allowed up to the
V
Output voltage
oscillator voltage.
VO2
Pins other than OSC2
–0.3 to VDD + 0.3
V
Input voltage
VIN
–0.3 to VDD + 0.3
V
Peak output current
IOP1
Audio interface, external RAM interface
–2 to +4
mA
1
IOP2
Microcontroller interface, P3, P4
–2 to +10
mA
2
IOA1
Audio interface, external RAM interface: per pin
–2 to +4
mA
1
IOA2
Microcontroller interface, P3, P4: per pin
–2 to +10
mA
2
Average output current
ΣI
OA1
Total for FS384O, LRCKO, BCKO, and ASO
–10 to +10
mA
ΣI
OA2
Total for DWRT, DREAD, RAS, CAS, A3 to A8
–30 to +30
mA
and D0 to D7
ΣI
OA3
Total for A0 to A2, SIAK, P3 and P4
–10 to +10
mA
Allowable power dissipation
Pd max
Ta = –30 to +70°C
700
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
Operating supply voltage
VDD
4.75
5.25
V
VIH1
Audio interface, external RAM interface
2.4
V
4
Input high level voltage
VIH2
P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5
0.7 VDD
V5
VIH3
RES, OSC1, microcontroller interface
0.75 VDD
V6
VIL1
Audio interface, external RAM interface
0.8
V
4
Input low level voltage
VIL2
P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5
0.3 VDD
V5
VIL3
RES, OSC1, microcontroller interface
0.25 VDD
V6
Instruction cycle time
tCYC
58
59.11
ns
[External Clock Input Conditions]
Frequency
fEXT
16.85
17.01
MHz
Pulse width
tEXTH
23
ns
tEXTL
23
ns
Rise time
tEXTR
9ns
Fall time
tEXTF
9ns
[Self-Excitation Oscillation Conditions]
Oscillator frequency
fOSC
OSC1 and OSC2: shown in Figure 2.
33.84
33.90
MHz
44.1 kHz
× 768 × ± 0.1%
Oscillator stabilization period
fOSCS
Shown in Figure 3.
100
ms
[Audio Data Input Conditions]
Transfer bit clock period
tBCYC
354
ns
Transfer bit clock pulse width
tBCW
Related to the BCKI and ASI pins. Shown in Figure 4.
100
ns
Data setup time
tS
70
ns
Data hold time
tH
70
ns
[Serial Input Clock Conditions]
Serial clock period
tSCYC
480
ns
Serial clock pulse width
tSCW
200
ns
Data setup time
tSS
Related to the microcontroller interface. Shown in
70
ns
Data hold time
tSH
Figure 5. (Related to the SICK, SI and SRDY pins.)
70
ns
SRDY hold time
tSYH
200
ns
SRDY pulse width
tSYW
200
ns
[DRAM Input Conditions]
Input data setup time
tDSI
Related to external DRAM data input. Shown in Figure 6.
20
ns
Input data hold time
tDHI
(Related to the CAS and D0 to D7 pins.)
0ns
Related to the FS384I pin. Shown in Figure 1.
max: 44.1 kHz
× 384 × 1.005
min: 44.1 kHz
× 384 × 0.995
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