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參數(shù)資料
| 型號： | LC83015E |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 307K |
| 代理商： | LC83015E |
LC83015E
No.4013–9/13
External Pseudo-SRAM Input Timing
External Pseudo-SRAM Output Timing
Design Notes
When SELC is LOW, the LC83015E system clock is gener-
ated from FS384I. When SELC is HIGH, it is generated
from the free-running oscillator, OSC1. When SACK1 is
LOW, FS384O output is 1/3 of FS128O output. When
SACK1 is HIGH, it is 1/4 of FS128O output. When SACK2
is LOW, the output clock is generated from FS384I, LRCKI
and BCK1. When SACK2 is HIGH, it is generated from the
free-running oscillator, OSC1.
When the LC83015E is used with one DRAM unit, only
D0 to D3 of the data bus are used. When the LC83015E is
used with two DRAM units, SRAM or pseudo-SRAM, D0
to D7 are used.
The typical supply current, IDD, is measured with SANYO
Standard Theatre Mode in operation under the input/output
conditions shown in figure 1.
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