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參數(shù)資料
| 型號(hào)： | LC8213K |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Image Data Compression/Expansion Processor(圖象數(shù)據(jù)壓縮/擴(kuò)展處理器) |
| 中文描述： | 圖像數(shù)據(jù)壓縮/擴(kuò)展處理器（圖象數(shù)據(jù)壓縮/擴(kuò)展處理器） |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 56K |
| 代理商： | LC8213K |
Switching Characteristics
at V
DD
= 2.7 to 5.5 V, Ta = –20 to +75°C, V
SS
= 0 V
I: Input pin O: Output pin B: Bi-directional pin P: Power supply pin NC: No connection
No. 5753-3/5
LC8213K
Pin No.
Pin name
I/O
Function
1
CS
I
Chip select signal
2
RD
I
Read signal from the CPU
3
WR
I
Write signal from the CPU
4
A2
I
5
A1
I
Address inputs
6
A0
I
7
V
DD
P
Power supply
8
NC
9
D7
B
10
D6
B
Data bus
11
D5
B
12
D4
B
13
V
SS
D3
P
Ground
14
B
15
D2
B
Data bus
16
D1
B
17
D0
B
18
NC
19
V
DD
IREQ
P
Power supply
20
O
Interrupt request signal
21
DREQ
O
DMA request signal output to external DMA controller
22
DACK
I
DMA acknowledge signal input from external DMA controller
23
NC
24
NC
25
NC
26
NC
27
RESET
I
Reset signal input
28
CLK
I
Clock input
29
V
SS
TEST4
P
Ground
30
I
Test pin
31
V
DD
TEST3
P
Power supply
32
I
33
TEST2
I
Test pin
34
TEST1
I
35
TEST0
I
36
NC
37
BREQ
O
Bus request signal for the image bus
38
BACK
I
Acknowledge signal for the image bus
39
IDREQ
I
DMA request signal from I/O devices
40
IDACK
O
DMA acknowledge signal to I/O devices
41
AEN
O
Address enable
42
AST
O
Address strobe
43
MDEN
O
Memory data enable
44
MRD
O
Image memory read signal
45
MWR
O
Image memory write signal
46
IORD
O
I/O device read signal
47
IOWR
O
I/O device write signal
48
LDE
O
Image bus lower byte valid signal
49
UDE
O
Image bus upper byte valid signal
50
READY
I
Ready signal
Continued on next page.
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