
No. 5521-10/22
LC7874E
Pin Functions
Pin
Pin Symbol
Pin Name
I/O
Polarity
Function
1
S1
CD DSP selection pins
In
Positive
2
S2
3
SBCK
Clock output pin
Out
—
Subcode R to W read clock output
4
SFSY
Sync signal input pin
In
Positive
Subcode frame sync signal input (MORE+ input)
5
PW
Data input pin
In
Positive
Subcode R to W data input (MORE+ input)
6
SBSY
Sync signal input pin
In
Positive
Subcode block sync signal input (MORE+ input)
7
V
DD
CE
Power supply pin (+5 v)
—
—
Digital power supply
8
Enable input pin
In
Positive
Serial input/output data control input (MORE+ input)
9
DO
Data output pin
Out
Positive
Serial data output (Nch open-drain)
10
DI
Data input pin
In
Positive
Serial data input (MORE+ input)
11
CL
Clock input pin
In
Positive
Serial data input/output clock input (MORE+ input)
12
MUTE
Data input pin
In
Positive
Control signal input invalidating subcode data (MORE+ input)
13
V
SS
CB
Ground pin (GND)
—
—
GND
14
Color bar selection pin
In
Positive
L: Normal mode, H: Color bar output (built-in pull-down resistor)
15
CDGM
Graphic data discrimination output pin
Out
Positive
Goes high when graphics data is input (can be reset low by command
control).
16
CE1
DRAM control input pin
In
Positive
Signal input setting DRAM connection pin to high impedance (MORE+
input)
17
A0
DRAM output pin
I/O
Positive
DRAM address (A0) output
18
A1
DRAM output pin
I/O
Positive
DRAM address (A1) output
19
A2
DRAM output pin
I/O
Positive
DRAM address (A2) output
20
A3
DRAM output pin
I/O
Positive
DRAM address (A3) output
21
A4
DRAM output pin
I/O
Positive
DRAM address (A4) output
22
A5
DRAM output pin
I/O
Positive
DRAM address (A5) output
23
A6
DRAM output pin
I/O
Positive
DRAM address (A6) output
24
A7
DRAM output pin
I/O
Positive
DRAM address (A7) output
25
CAS
DRAM output pin
3ST
Negative DRAM column address strobe signal output
26
WE
DRAM output pin
3ST
Negative DRAM data write enable signal output
27
OE
DRAM output pin
3ST
Negative DRAM data read enable signal output
28
RAS
DRAM output pin
3ST
Negative DRAM row address strobe signal output
29
DB0
DRAM input/output pin
I/O
Positive
DRAM data (D0) input/output
30
DB1
DRAM input/output pin
I/O
Positive
DRAM data (D1) input/output
31
DB2
DRAM input/output pin
I/O
Positive
DRAM data (D2) input/output
32
DB3
DRAM input/output pin
I/O
Positive
DRAM data (D3) input/output
33
BLANK
Blank signal output pin
3ST
Positive
Video signal blanking period output
34
CSYNC
Composite sync output pin
3ST
Negative Composite sync signal output
S1
S2
Selected CD DSP
0
0
LC7861N/67
1
0
LC7860K/63
0
1
Setting prohibited
1
1
LC7868/62X/63X
Continued on next page.