
LC78684E
No.7350-18/21
Continued from preceding page.
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
Pin Name
DV
DD
4
V
SS
MADRS7
MADRS6
MADRS5
MADRS4
MADRS3
MADRS2
MADRS1
MADRS0
DV
DD
5
V
SS
I/O
Block
Function
Digital I/O system power supply
Ground
DRAM address output 7
DRAM address output 6
DRAM address output 5
DRAM address output 4
DRAM address output 3
DRAM address output 2
DRAM address output 1
DRAM address output 0
Internal logic system power supply
GND
MP3 data request flag output (active high)
/DRAM data request flag input (CD-ROM mode, active high)
MP3 data transfer clock input
/DRAM data transfer clock output
MP3 serial data input
/DRAM serial data output
MP3 frame sync signal (active high)
/Data continuity point detection complete flag (CD-DA mode, active high)
CRC check result output (CD-ROM data/CD-DA subcode data)
/DRAM data output enable signal output (active high)
Digital I/O system power supply
GND
DRAM write enable input (CD-DA mode, active high)
/DRAM data request flag input
Data continuity point detection complete flag (CD-DA mode, active high)
/SYNC error monitor flag (MP3 mode, active high)/DRAM serial data output
DRAM write interrupt flag (CD-DA mode, active high)
/Emphasis output flag (CD-DA and MP3 modes, active high)
/DRAM data transfer clock output
Serial command data output (n-channel open-drain output)
Serial command data input
Serial command clock input
Command enable input (active high)
Interrupt signal output (active low)
/DRAM write interrupt flag (CD-DA mode, active high)
System reset (active low)
Serial CD data input
CD bit clock input
Power supply
O
O
O
O
O
O
O
O
Memory interface
Power supply
63
STREQ
I/O
64
STCK
I/O
65
STDAT
I/O
MP3 stream I/O
66
FSYNC
O
MP3-dec
67
CRCF
O
CD monitor
68
69
DV
DD
6
V
SS
Power supply
70
WOK
I
71
CNTOK
O
72
OVF
O
CD-DA shockproof
and MP3 I/O
73
74
75
76
CMDOUT
CMDIN
CL
CE
O
I
I
I
77
INTB
O
78
79
80
RESB
DATAIN
DATACK
I
I
I
Microcontroller
interface
CD IF
Notes: 1. Notes on unused pins.
Unused input pins must be connected to the ground level (0 V).
Unused output pins must be left open. Do not connect anything to these pins.
Unused I/O pins may either be connected to the ground level (0 V) or set to output mode and left open.
2. The corresponding power supply levels must be provided to all of the DV
DD
1, DV
DD
3, DV
DD
4, DV
DD
6, and AV
DD
pins. The
corresponding power supply level must also be provided to DV
DD
2 and DV
DD
5. (See the Allowable Operating Ranges specifications
for the supply levels.)
3. The TEST1 and TEST2 input pins must be connected to ground (0 V).
4. The I/O pins (MDAT0:15, STREQ, STCK, and STDAT) go to input mode after a reset.
5. After first applying the power supply levels, the RESB pin must be held low for at least 1 μs.
6. A 16.9344 MHz clock signal must be supplied to the CKIN pin by the CD DSP.
The LC78684E does not support the implementation of an oscillator circuit using an oscillator element.