參數(shù)資料
型號(hào)： LC78625E
廠商： Sanyo Electric Co.,Ltd.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述： SigmaDSP的28-/56-Bit音頻處理器雙ADC和4個(gè)DAC
文件頁(yè)數(shù)： 9/35頁(yè)
文件大?。?/td> 440K
代理商： LC78625E
No. 5502-9/35
LC78625E
Continued from preceding page.
Pin No.
Symbol
I/O
Function
38
ASDACK/P0
I/O
Bit clock input
39
ASDFIN/P1
I/O
Left and right channel data input
40
ASDEPC/P2
I/O
Sets the built-in de-emphasis filter on or off.
(High: on, low: off)
41
ASLRCK/P3
I/O
L/R clock input
42
LRSY
O
L/R clock output
43
CK2
O
Bit clock output
(after reset)
Inverted polarity clock output
(during CK2CON mode)
ROMXA application output signals
44
ROMXA
O
Interpolation data output
(after reset)
ROM data output (during ROMXA mode)
45
C2F
O
C2 flag output
46
MUTEL
O
Left channel mute output
47
LV
DD
LCHP
Left channel power supply
48
O
Left channel P output
49
LCHN
O
Left channel N output
50
LV
SS
RV
SS
RCHN
One-bit D/A converter signals
Left channel ground. Must be connected to 0 V.
51
Right channel ground. Must be connected to 0 V.
52
O
Right channel N output
53
RCHP
O
Right channel P output
54
RV
DD
MUTER
Right channel power supply
55
O
Right channel mute output
56
DOUT
O
Digital output
57
SBSY
O
Subcode block synchronization signal output
58
EFLG
O
C1, C2, single and double error correction monitor pin
59
PW
O
Subcode P, Q, R, S, T, U and W output
60
SFSY
O
Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state.
61
SBCK
I
Subcode readout clock input. This is a Schmitt input. (This pin must be connected to 0 V if unused.)
62
FSX
O
Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
63
WRQ
O
Subcode Q output standby output
64
RWC
I
Read/write control input. This is a Schmitt input.
65
SQOUT
O
Subcode Q output
66
COIN
I
Command input from the control microprocessor
67
CQCK
I
Input for the command input acquisition clock or the SQOUT pin subcode readout clock input. This is a Schmitt input.
68
RES
I
Reset input. This pin must be set low briefly after power is first applied.
69
TST11
O
Test output. Leave open. (Normally outputs a low level.)
70
LASER
O
Laser on/off output. Controlled by serial data commands from the control microprocessor.
71
16M
O
16.9344 MHz output
72
4.2M
O
4.2336 MHz output
73
CONT
O
Supplementary control output. Controlled by serial data commands from the control microprocessor.
74
TEST5
I
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
75
CS
I
Chip select input. A pull-down resistor is built in. This pin must be connected to 0 V if unused.
76
XV
SS
XIN
Crystal oscillator ground. Must be connected to 0 V.
77
I
Connections for a 16.9344 MHz crystal oscillator
78
XOUT
O
79
XV
DD
TEST1
Crystal oscillator power supply
80
I
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
When antishock mode is not used,
these pins are used as general-
purpose I/O ports (P0 to P3). They
must either be set to input mode and
connected to 0 V, or set to output
mode and left open, if unused.
The antishock inputs in
antishock mode.
Note: All power-supply pins (V
DD
, VV
DD
, LV
DD
, RV
DD
, and XV
DD
) must be connected to the same potential.
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