
14. Interpolation Circuit
Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result
in loud noises being output. To minimize this noise, the LC78620E replaces the incorrect data with linearly
interpolated data based on the correct data on either side of the incorrect data. More precisely, the LC78620E uses
this technique if C2 flags occurred up to three times in a row. If C2 flags occurred four or more times in a row, the
LC78620E converges the output level to the muting level. However, when correct data is finally output following
four or more C2 flag occurrences, the LC78620E replaces the 3 data items between the data output three items
previously and the correct data with data linearly interpolated data.
15. Bilingual Function
 Following a reset or when a stereo (28H) command has been issued, the left and right channel data is output to the
left and right channels respectively.
 When an Lch set (29H) command is issued, the left and right channels both output the left channel data.
 When an Rch set (2AH) command is issued, the left and right channels both output the right channel data.
16. De-Emphasis; Pin 32: EMPH
The preemphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is
high, the LC78620E internal de-emphasis circuit operates and the digital filters and the D/A converter output de-
emphasized data.
17. Digital Attenuator
Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding
two-byte command to the COIN pin in synchronization with the CQCK clock.
No. 5130-22/34
LC78620E
MSB
LSB
Command
RES = low
G
 G
0 0 1 0 1 0 0 0
STO CONT
0 0 1 0 1 0 0 1
Lch CONT
0 0 1 0 1 0 1 0
Rch CONT
MSB
LSB
Command
RES = low
1 0 0 0 0 0 0 1
ATT DATA SET
DATA 00H set
(MUTE –
∞
 dB)
1 0 0 0 0 0 1 0
ATT 4 STEP UP
1 0 0 0 0 0 1 1
ATT 4 STEP DOWN
1 0 0 0 0 1 0 0
ATT 8 STEP UP
1 0 0 0 0 1 0 1
ATT 8 STEP DOWN
1 0 0 0 0 1 1 0
ATT 16 STEP UP
1 0 0 0 0 1 1 1
ATT 16 STEP DOWN