
No. 5755-4/13
LC78011E
Continued from preceding page.
Pin No.
Symbol
I/O
Polarity
Function
40
BLANK
IN
Positive
Composite blanking signal input (HBLANK + VBLANK)
41
CSYNC
IN
Negative Composite synchronizing signal input (HSYNC + VSYNC)
42
HSYNC
IN
Negative Horizontal synchronizing signal input (HSYNC)
43
YUVSEL1
IN
Positive
Signal input setup
44
YUVSEL2
IN
Positive
45
RYIN7
IN
Positive
R/Y data input (MSB)
A pull-down resistor is built in.
46
RYIN6
IN
Positive
R/Y data input
A pull-down resistor is built in.
47
RYIN5
IN
Positive
R/Y data input
A pull-down resistor is built in.
48
RYIN4
IN
Positive
R/Y data input
A pull-down resistor is built in.
YUVSEL1 YUVSEL2
Video signal input signal mode
0
0
RYIN = R in, GUIN = G in, BVIN = B in
1
0
RYIN = Y in, GUIN = U in, BVIN = V in
0
1
RYIN = Y in, GUIN = none, BVIN = UV in
1
1
— (Illegal setting)
Notes:1. The voltage applied as the digital system power supply voltage must not exceed the voltage applied as the analog system power supply voltage.
2. Unused input pins must be tied high or low. If the OSD inputs are not used, tie OSBLK (pin 39) low.
3. Note that the clock input frequencies (CLKI: pin 6, and FSCIN: pin 7) depend on the TV subcarrier pull-in range. The CLKI input clock and the
FSCIN clock must be synchronized.
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
1 max
V
DD
2 max
DV
DD
(DV
DD
≤
AV
DD
)
AV
DD
RYIN0 to RYIN7, GUIN0 to GUIN7,
BVIN0 to BVIN7, CLKI, FSCIN,
OSRIN, OSGIN, OSBIN, OSBLK,
BLANK, CSYNC, HSYNC, RESET,
CCSEL, NPSEL, PMSEL, CDGSEL,
YUVSEL1, YUVSEL2, and TEST
DV
SS
– 0.3 to DV
SS
+7.0
AV
SS
– 0.3 to AV
SS
+7.0
V
V
Input voltage
V
IN
DV
SS
– 0.3 to DV
DD
+0.3
V
Output voltage
V
OUT
Pd max
CROUT, YOUT, and BIAS
DV
SS
– 0.3 to DV
DD
+0.3
V
Allowable power dissipation
Ta = 25°C
500
mW
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
2
DV
DD
(DV
DD
≤
AV
DD
)
AV
DD
OSRIN, OSGIN, OSBIN, OSBLK
CCSEL, NPSEL, PMSEL, CDGSEL,
YUVSEL1, YUVSEL2, TEST
3.0
5.5
V
4.5
5.0
5.5
V
V
IH
1
0.7 V
DD
1
V
DD
1 + 0.3
V
Input high-level voltage
RYIN0 to RYIN7, GUIN0 to GUIN7,
BVIN0 to BVIN7, BLANK, CSYNC
HSYNC, RESET
V
IH
2
2.2
V
DD
1 + 0.3
V
OSRIN, OSGIN, OSBIN, OSBLK
CCSEL, NPSEL, PMSEL, CDGSEL,
YUVSEL1, YUVSEL2, TEST
V
IL
1
V
SS
1 – 0.3
0.3 V
DD
1
V
Input low-level voltage
RYIN0 to RYIN7, GUIN0 to GUIN7,
BVIN0 to BVIN7, BLANK, CSYNC
HSYNC, RESET
V
IL
2
V
SS
1 – 0.3
0.8
V
NTSC
14.31818
MHz
f
IN
1
CLKI
PAL
17.734475
MHz
Clock frequency
PAL-M
14.3024459
MHz
NTSC
3.579545
MHz
f
IN
2
FSCIN
PAL
4.43361875
MHz
PAL-M
3.57561149
MHz
Allowable Operating Ranges
at Ta = –20 to 75°C unless otherwise specified
Continued on next page.